Datasheet LTC3407-4 (Analog Devices) - 6

LTC3407-4
BLOCK DIAGRAM
REGULATOR 1 MODE/SYNC 6 BURST CLAMP VIN SLOPE COMP – EN 0.6V + I SLEEP – + TH 5Ω EA ICOMP 0.35V + V 1 FB1 – BURST S Q RS LATCH R Q 0.55V – SWITCHING UV UVDET LOGIC AND + BLANKING ANTI CIRCUIT SHOOT- THRU 4 SW1 + OV OVDET 0.65V – + IRCMP SHUTDOWN – 11 GND VIN 3 V PGOOD1 IN 8 POR RUN1 2 POR 0.6V REF OSC COUNTER RUN2 9 OSC 5 GND PGOOD2 REGULATOR 2 (IDENTICAL TO REGULATOR 1) V 10 7 SW2 FB2 34074 BD
OPERATION
The LTC3407-4 uses a constant frequency, current mode
Main Control Loop
architecture. The operating frequency is set at 2.25MHz During normal operation, the top power switch (P-channel and can be synchronized to an external oscillator. Both MOSFET) is turned on at the beginning of a clock cycle channels share the same clock and run in-phase. To suit a when the VFB voltage is below the the reference voltage. variety of applications, the selectable Mode pin allows the The current into the inductor and the load increases until user to choose between low noise and high effi ciency. the current limit is reached. The switch turns off and The output voltage is set by an external divider returned energy stored in the inductor fl ows through the bottom to the V switch (N-channel MOSFET) into the load until the next FB pins. An error amplifi er compares the divided output voltage with a reference voltage of 0.6V and adjusts clock cycle. the peak inductor current accordingly. Overvoltage and The peak inductor current is controlled by the internally undervoltage comparators will pull the POR output low if compensated ITH voltage, which is the output of the er- the output voltage is not within ±8.5%. The POR output ror amplifi er. This amplifi er compares the VFB pin to the will go high after 216 clock cycles (about 29ms in pulse- 0.6V reference. When the load current increases, the skipping mode) of achieving regulation. VFB voltage decreases slightly below the reference. This 34074fa 6