Datasheet LT3506, LT3506A (Analog Devices) - 7

LT3506/LT3506A
OPERATION (Refer to the Block Diagram)
The LT3506 is a dual, constant frequency, current mode the inductor fl ows through the external Schottky diode, buck regulator with internal 2A power switches. The two and begins to decrease. The cycle begins again at the next regulators share common circuitry including voltage pulse from the oscillator. In this way the voltage on the VC reference and oscillator. In addition, the analog blocks pin controls the current through the inductor to the output. on both regulators share the VIN1 supply voltage, but are The internal error amplifi er regulates the output voltage otherwise independent. This section describes the opera- by continually adjusting the VC pin voltage. tion of the LT3506. The threshold for switching on the VC pin is 0.75V, and an If the RUN/SS (run/soft-start) pins are both tied to ground, active clamp of 1.9V limits the output current. The VC pin the LT3506 is shut down and draws 30μA from VIN1. is also clamped to the RUN/SS pin voltage. As the internal Internal 2μA current sources charge external soft-start current source charges the external soft-start capacitor, capacitors, generating voltage ramps at these pins. If either the current limit increases slowly. Each switcher contains RUN/SS pin exceeds 0.6V, the internal bias circuits turn an independent oscillator. This slave oscillator is normally on, including the internal regulator, 800mV reference and synchronized to the master oscillator. However, during 575kHz master oscillator. In this state, the LT3506 draws start-up, short-circuit or overload conditions, the FB pin 3.8mA from VIN1, whether one or both RUN/SS pins are voltage will be near zero and an internal comparator gates high. Neither switching regulator will begin to operate the master oscillator clock signal. This allows the slave until its RUN/SS pin reaches ~0.8V. The master oscillator oscillator to run the regulator at a lower frequency. This generates two clock signals of opposite phase. frequency foldback behavior helps to limit switch current The two switchers are current mode, step-down regulators. and power dissipation under fault conditions. This means that instead of directly modulating the duty The switch driver operates from either the input or from cycle of the power switch, the feedback loop controls the the BOOST pin. An external capacitor and diode are used peak current in the switch during each cycle. This cur- to generate a voltage at the BOOST pin that is higher than rent mode control improves loop dynamics and provides the input supply. This allows the driver to fully saturate cycle-by-cycle current limit. the internal bipolar NPN power switch for effi cient opera- The Block Diagram in Figure 2 shows only one of the two tion. switching regulators. A pulse from the slave oscillator A power good comparator trips when the FB pin is at 90% sets the RS fl ip-fl op and turns on the internal NPN bipolar of its regulated value. The PG output is an open collector power switch. Current in the switch and the external induc- transistor that is off when the output is in regulation, al- tor begins to increase. When this current exceeds a level lowing an external resistor to pull the PG pin high. Power determined by the voltage at VC, current comparator C1 good is valid when the LT3506 is enabled (either RUN/SS resets the fl ip-fl op, turning off the switch. The current in pin is high) and VIN is greater than ~3.4V. 3506afc 7