Datasheet LTC3543 (Analog Devices) - 9

LTC3543
OPERATION
–10 –10 RBW = 3kHz RBW = 3kHz –20 –20 –30 –30 –40 –40 –50 –50 –60 –60 –70 –70 AMPLITUDE (dBm) –80 AMPLITUDE (dBm) –80 –90 –90 –100 –100 –110 –110 2.0 2.2 2.4 2.6 2.8 3.0 2.0 2.2 2.4 2.6 2.8 3.0 FREQUENCY (MHz) FREQUENCY (MHz) 3543 F01a 3543 F01b
Figure 1a. Output Noise Spectrum of Conventional Buck Switching Figure 1b. Output Noise Spectrum of the LTC3543 Spread Spectrum Converter (LTC3543 with Spread Spectrum Disabled) Showing Buck Switching Converter. Note the Reduction in Fundamental and Fundamental and Harmonic Frequencies Harmonic Peak Spectral Amplitude Compared to Figure 1a.
Unlike conventional buck converters, the LTC3543’s inter- Selecting the switching frequency is a trade-off between nal oscillator is designed to produce a clock pulse whose effi ciency and component size. Low frequency opera- frequency is randomly varied between 2MHz and 3MHz. tion increases effi ciency by reducing MOSFET switching This has the benefi t of spreading the switching noise over losses, but requires larger inductance and/or capacitance a range of frequencies, signifi cantly reducing the peak to maintain low output ripple voltage. noise. Figure 1b shows the output noise spectrum of the Note that the PLL is inhibited during soft-start and uses LTC3543 (with spread spectrum operation enabled) with VIN the internal 2.25MHz frequency until regulation is estab- = 3.6V, VOUT = 1.5V and IOUT = 300mA. Note the signifi cant lished. Also the regulator is in pulse skip mode during reduction in peak output noise (≅ 20dBm). PLL operation.
Phase-Locked Loop Operation Short-Circuit Protection
A phase-locked loop (PLL) is available on the LTC3543 When the output is shorted to ground, the LTC3543 senses to synchronize the internal oscillator to an external clock the high inductor current and disallows the main power source that is connected to the MODE pin. In this case, an FET from turning on. The main FET is held off until the external capacitor should be connected between the CAP inductor current decays to a normal level. pin and GND to serve as part of the PLL’s loop fi lter. The LTC3543’s phase detector adjusts the voltage on the CAP
Dropout Operation
pin to align the turn-on of the internal P-channel MOSFET to the rising edge of the synchronizing signal. Note that Depending upon the external feedback resistor ratio, it is when the MODE pin is not being driven by an external possible for VIN to approach the output voltage level. As clock source, the MODE pin must be held to one of the the input supply voltage decreases to a value approaching following voltage potentials: V the output voltage, the duty cycle increases toward the IN, GND, or VFB. maximum on-time. Further reduction of the supply voltage The typical capture range of the LTC3543 ’s PLL is guar- forces the main switch to remain on for more than one cycle anteed over temperature to be 1MHz to 3MHz. In other until it reaches 100% duty cycle. The output voltage will words, the LTC3543’s PLL is guaranteed to lock to an then be determined by the input voltage minus the voltage external clock source whose frequency is between 1MHz drop across the P-channel MOSFET and the inductor. and 3MHz. 3543fa 9