Datasheet LTC3672B-2 (Analog Devices) - 6
| Hersteller | Analog Devices |
| Beschreibung | Monolithic Fixed-Output 400mA Buck Regulator with Dual 150mA LDOs in 2mm × 2mm DFN |
| Seiten / Seite | 12 / 6 — PIN FUNCTIONS. SW (Pin 1):. LDO1 (Pin 6):. GND (Pin 2):. LDO2 (Pin 7):. … |
| Dateiformat / Größe | PDF / 161 Kb |
| Dokumentensprache | Englisch |
PIN FUNCTIONS. SW (Pin 1):. LDO1 (Pin 6):. GND (Pin 2):. LDO2 (Pin 7):. ENALL (Pin 3):. VIN (Pin 8):. BUCKOUT (Pin 4):. VIN1 (Pin 5):
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LTC3672B-2
PIN FUNCTIONS SW (Pin 1):
Switch Node Connection to Inductor. This pin
LDO1 (Pin 6):
Output of the First Low Dropout Linear connects to the drains of the buck regulator’s main PMOS Regulator. This pin must be bypassed to ground with a and synchronous NMOS switches. 1μF or greater ceramic capacitor.
GND (Pin 2):
Ground.
LDO2 (Pin 7):
Output of the Second Low Dropout Linear Regulator. This pin must be bypassed to ground with a
ENALL (Pin 3):
Enables all three outputs when high, shuts 1μF or greater ceramic capacitor. down the IC when low. This is a MOS gate input. An internal 5.5MΩ resistor pulls this pin to ground.
VIN (Pin 8):
Input Bias Supply for the IC, and Power Input for the Buck Regulator and LDO2. This pin should
BUCKOUT (Pin 4):
Output Voltage Sense Connection for be bypassed to ground with a 2.2μF or greater ceramic the Buck Regulator. capacitor.
VIN1 (Pin 5):
Power Input for the First Low Dropout Linear
Exposed Pad (Pin 9):
Ground. The Exposed Pad must be Regulator, LDO1. This pin may be connected to VIN (Pin 8), soldered to PCB ground. or to a voltage never exceeding VIN.
BLOCK DIAGRAM
4 8 5 BUCKOUT V V LDO1 IN IN1 6 LDO2 400mA BUCK + 7 SW 1 400k 2M 1M – GND 800k 800k 800k 2 LDO2 LDO1 ENABLE BUCK 2.25MHz OSC 800mV LOGIC REFERENCE ENALL 3 5.5M ENABLE LDO2 ENABLE LDO1 EXPOSED PAD (GND) 9 3672B2 BD 3672b2fa 6
PIN FUNCTIONS SW (Pin 1):
Switch Node Connection to Inductor. This pin
LDO1 (Pin 6):
Output of the First Low Dropout Linear connects to the drains of the buck regulator’s main PMOS Regulator. This pin must be bypassed to ground with a and synchronous NMOS switches. 1μF or greater ceramic capacitor.
GND (Pin 2):
Ground.
LDO2 (Pin 7):
Output of the Second Low Dropout Linear Regulator. This pin must be bypassed to ground with a
ENALL (Pin 3):
Enables all three outputs when high, shuts 1μF or greater ceramic capacitor. down the IC when low. This is a MOS gate input. An internal 5.5MΩ resistor pulls this pin to ground.
VIN (Pin 8):
Input Bias Supply for the IC, and Power Input for the Buck Regulator and LDO2. This pin should
BUCKOUT (Pin 4):
Output Voltage Sense Connection for be bypassed to ground with a 2.2μF or greater ceramic the Buck Regulator. capacitor.
VIN1 (Pin 5):
Power Input for the First Low Dropout Linear
Exposed Pad (Pin 9):
Ground. The Exposed Pad must be Regulator, LDO1. This pin may be connected to VIN (Pin 8), soldered to PCB ground. or to a voltage never exceeding VIN.
BLOCK DIAGRAM
4 8 5 BUCKOUT V V LDO1 IN IN1 6 LDO2 400mA BUCK + 7 SW 1 400k 2M 1M – GND 800k 800k 800k 2 LDO2 LDO1 ENABLE BUCK 2.25MHz OSC 800mV LOGIC REFERENCE ENALL 3 5.5M ENABLE LDO2 ENABLE LDO1 EXPOSED PAD (GND) 9 3672B2 BD 3672b2fa 6