Datasheet LT3682 (Analog Devices) - 8
| Hersteller | Analog Devices |
| Beschreibung | 1A Micropower Step-Down Switching Regulator |
| Seiten / Seite | 24 / 8 — PIN FUNCTIONS. VC (Pin 1):. SW (Pin 8):. RUN/SS (Pin 9):. FB (Pin 2):. PG … |
| Dateiformat / Größe | PDF / 265 Kb |
| Dokumentensprache | Englisch |
PIN FUNCTIONS. VC (Pin 1):. SW (Pin 8):. RUN/SS (Pin 9):. FB (Pin 2):. PG (Pin 3):. RT (Pin 10):. SYNC (Pin 11):. GND (Pin 4):
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LT3682
PIN FUNCTIONS VC (Pin 1):
The VC pin is the output of the internal error
SW (Pin 8):
The SW pin is the output of the internal power amplifi er. The voltage on this pin controls the peak switch switch. Connect this pin to the inductor, catch diode and current. Tie an RC network from this pin to ground to boost capacitor. compensate the control loop.
RUN/SS (Pin 9):
The RUN/SS pin is used to put the LT3682
FB (Pin 2):
The LT3682 regulates the FB pin to 0.8V. Connect in shutdown mode. Tie to ground to shut down the LT3682. the feedback resistor divider tap to this pin. Tie to 2.5V or more for normal operation. RUN/SS also provides a soft-start function; see the Applications Infor-
PG (Pin 3):
The PG pin is the open collector output of an mation section for more information. internal comparator. PG remains low until the FB pin is within 10% of the fi nal regulation voltage. PG output is
RT (Pin 10):
Oscillator Resistor Input. Connect a resistor valid when VIN is above the minimum input voltage and from this pin to ground to set the switching frequency. RUN/SS is high.
SYNC (Pin 11):
This is the external clock synchronization
GND (Pin 4):
The GND pin is the ground of all the internal input. Ground this pin for low ripple Burst Mode operation circuitry. Tie directly to the local GND plane. at low output loads. Tie to 0.8V or more for pulse skipping mode operation. Tie to a clock source for synchronization.
BD (Pin 5):
This pin connects to the anode of the boost Clock edges should have rise and fall times faster than Schottky diode. BD also supplies current to the LT3682’s 1μs. Note that the maximum load current depends on internal regulator. which mode is chosen. See the Applications Information
BOOST (Pin 6):
This pin is used to provide a drive volt- section for more information. age, higher than the input voltage, to the internal bipolar
V
NPN power switch. Connect a capacitor (typically 0.22μF)
IN (Pin 12):
The VIN pin supplies current to the LT3682’s internal regulator and to the internal power switch. This between BOOST and SW. pin must be locally bypassed.
DA (Pin 7):
Connect the anode of the catch diode (D1
Exposed Pad (Pin 13):
PGND. This is the power ground used in Block Diagram) to this pin. Internal circuitry senses by the catch diode (D1) when its anode is connected to the the current through the catch diode providing frequency DA pin. The exposed pad must be soldered to the PCB. foldback in extreme situations. 3682f 8
PIN FUNCTIONS VC (Pin 1):
The VC pin is the output of the internal error
SW (Pin 8):
The SW pin is the output of the internal power amplifi er. The voltage on this pin controls the peak switch switch. Connect this pin to the inductor, catch diode and current. Tie an RC network from this pin to ground to boost capacitor. compensate the control loop.
RUN/SS (Pin 9):
The RUN/SS pin is used to put the LT3682
FB (Pin 2):
The LT3682 regulates the FB pin to 0.8V. Connect in shutdown mode. Tie to ground to shut down the LT3682. the feedback resistor divider tap to this pin. Tie to 2.5V or more for normal operation. RUN/SS also provides a soft-start function; see the Applications Infor-
PG (Pin 3):
The PG pin is the open collector output of an mation section for more information. internal comparator. PG remains low until the FB pin is within 10% of the fi nal regulation voltage. PG output is
RT (Pin 10):
Oscillator Resistor Input. Connect a resistor valid when VIN is above the minimum input voltage and from this pin to ground to set the switching frequency. RUN/SS is high.
SYNC (Pin 11):
This is the external clock synchronization
GND (Pin 4):
The GND pin is the ground of all the internal input. Ground this pin for low ripple Burst Mode operation circuitry. Tie directly to the local GND plane. at low output loads. Tie to 0.8V or more for pulse skipping mode operation. Tie to a clock source for synchronization.
BD (Pin 5):
This pin connects to the anode of the boost Clock edges should have rise and fall times faster than Schottky diode. BD also supplies current to the LT3682’s 1μs. Note that the maximum load current depends on internal regulator. which mode is chosen. See the Applications Information
BOOST (Pin 6):
This pin is used to provide a drive volt- section for more information. age, higher than the input voltage, to the internal bipolar
V
NPN power switch. Connect a capacitor (typically 0.22μF)
IN (Pin 12):
The VIN pin supplies current to the LT3682’s internal regulator and to the internal power switch. This between BOOST and SW. pin must be locally bypassed.
DA (Pin 7):
Connect the anode of the catch diode (D1
Exposed Pad (Pin 13):
PGND. This is the power ground used in Block Diagram) to this pin. Internal circuitry senses by the catch diode (D1) when its anode is connected to the the current through the catch diode providing frequency DA pin. The exposed pad must be soldered to the PCB. foldback in extreme situations. 3682f 8