Datasheet LTC3633 (Analog Devices) - 8

LTC3633
PIN FUNCTIONS (QFN/TSSOP) PGOOD1 (Pin 1/Pin 4):
Channel 1 Open-Drain Power ance once the VFB2 pin returns to within ±5% (typical) of Good Output Pin. PGOOD1 is pulled to ground when the the internal reference. voltage on the VFB1 pin is not within ±8% (typical) of the
V
internal 0.6V reference. PGOOD1 becomes high imped-
FB2 (Pin 9/Pin 12):
Channel 2 Output Feedback Voltage Pin. Input to the error amplifier that compares the feedback ance once the VFB1 pin returns to within ±5% (typical) of voltage to the internal 0.6V reference voltage. Connect this the internal reference. pin to a resistor divider network to program the desired
PHMODE (Pin 2/Pin 5):
Phase Select Input. Tie this pin output voltage. to ground to force both channels to switch in phase. Tie
TRACKSS2 (Pin 10/Pin 13):
Output Tracking and Soft-Start this pin to INTVCC to force both channels to switch 180° Input Pin for Channel 2. Forcing a voltage below 0.6V on out of phase. Do not float this pin. this pin bypasses the internal reference input to the error
RUN1 (Pin 3/Pin 6):
Channel 1 Regulator Enable Pin. amplifier. The LTC3633 will servo the FB pin to the TRACK Enables channel 1 operation by tying RUN1 above 1.22V. voltage under this condition. Above 0.6V, the tracking func- Tying it below 1V places channel 1 into shutdown. Do not tion stops and the internal reference resumes control of float this pin. the error amplifier. An internal 1.4µA pull up current from
MODE/SYNC (Pin 4/Pin 7):
Mode Select and External INTVCC allows a soft start function to be implemented by Synchronization Input. Tie this pin to ground to force connecting a capacitor between this pin and SGND. continuous synchronous operation at all output loads.
ITH2 (Pin 11/Pin 14):
Channel 2 Error Amplifier Output Floating this pin or tying it to INTVCC enables high efficiency and Switching Regulator Compensation Pin. Connect this Burst Mode operation at light loads. Drive this pin with a pin to appropriate external components to compensate clock to synchronize the LTC3633 switching. An internal the regulator loop frequency response. Connect this pin phase-locked loop will force the bottom power NMOS’s to INTVCC to use the default internal compensation. turn on signal to be synchronized with the rising edge of
V
the CLKIN signal. When this pin is driven with a clock,
ON2 (Pin 12/Pin 15):
On-Time Voltage Input for Chan- nel 2. This pin sets the voltage trip point for the on-time forced continuous mode is automatically selected. comparator. Tying this pin to the output voltage makes
RT (Pin 5/Pin 8):
Oscillator Frequency Program Pin. the on-time proportional to VOUT2 when VOUT2 < 6V. When Connect an external resistor (between 80k to 640k) from VOUT2 > 6V, switching frequency may become higher than this pin to SGND in order to program the frequency from the set frequency. The pin impedance is nominally 140kΩ. 500kHz to 4MHz. When RT is tied to INTVCC, the switching
SW2 (Pins 13, 14/Pins 16, 17):
Channel 2 Switch Node frequency will default to 2MHz. Connection to External Inductor. Voltage swing of SW is
RUN2 (Pin 6/Pin 9):
Channel 2 Regulator Enable Pin. from a diode voltage drop below ground to VIN. Enables channel 2 operation by tying RUN2 above 1.22V.
V
Tying it below 1V places channel 2 into shutdown. Do not
IN2 (Pins 15, 16/Pins 18, 19):
Power Supply Input for Channel 2. Input voltage to the on chip power MOSFETs float this pin. on channel 2. This input is capable of operating from a
SGND (Pin 7/Pin 10):
Signal Ground Pin. This pin should different supply voltage than VIN1. have a low noise connection to reference ground. The
BOOST2 (Pin 17/Pin 20):
Boosted Floating Driver Supply feedback resistor network, external compensation network, for Channel 2. The (+) terminal of the bootstrap capacitor and RT resistor should be connected to this ground. connects to this pin while the (–) terminal connects to
PGOOD2 (Pin 8/Pin 11):
Channel 2 Open-Drain Power the SW pin. The normal operation voltage swing of this Good Output Pin. PGOOD2 is pulled to ground when the pin ranges from a diode voltage drop below INTVCC up voltage on the VFB2 pin is not within ±8% (typical) of the to VIN+INTVCC. internal 0.6V reference. PGOOD2 becomes high imped- 3633fd 8 For more information www.linear.com/LTC3633 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Typical Performance Characteristics Pin Functions Block Diagram Operation Applications Information Typical Applications Package Description Revision History Typical Application Related Parts