Datasheet LT3686 (Analog Devices) - 10
| Hersteller | Analog Devices |
| Beschreibung | 37V/1.2A Step-Down Regulator in 3mm × 3mm DFN |
| Seiten / Seite | 28 / 10 — ApplicAtions inForMAtion. FB Resistor Network. Programmable Undervoltage … |
| Dateiformat / Größe | PDF / 527 Kb |
| Dokumentensprache | Englisch |
ApplicAtions inForMAtion. FB Resistor Network. Programmable Undervoltage Lockout. Figure 2. EN/UVLO Pin Current
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LT3686
ApplicAtions inForMAtion FB Resistor Network
45 The output voltage is programmed with a resistor divider 40 between the output and the FB pin. Choose the 1% resis- 35 tors according to: 30 25 ⎛ V R1 OUT ⎞ 20 = R2 – 1 EN/UVLO (µA) ⎝⎜ 0.8V ⎠⎟ 15 10 R2 should be 20k or less to avoid bias current errors. 5 Reference designators refer to the Block Diagram. 0 0 10 20 30 40 50
Programmable Undervoltage Lockout
EN/UVLO (V) 3686 F02 The EN/UVLO pin can be programmed by an external re-
Figure 2. EN/UVLO Pin Current
sistor divider between VIN and the EN/UVLO pin. Choose the resistors according to:
Input Voltage Range
V The input voltage range for the LT3686 applications depends R4=R5 IN – 1 on the output voltage and on the absolute maximum ratings 1.27V of the VIN and BOOST pins. The minimum input voltage R4 also sets the hysteresis voltage for the programmable is determined by either the LT3686’s minimum operating UVLO: voltage of 3.6V, or by its maximum duty cycle. Hysteresis = R4 • 2.4µA The duty cycle is the fraction of time that the internal switch is on and is determined by the input and output voltages: Once VIN drops below the programmed voltage, the LT3686 will enter a low quiescent current state (I V Q ≈ 15µA). To DC= OUT + VD shutdown the LT3686 completely (IQ < 1µA), reduce EN/ VIN – VSW + VD UVLO pin voltage to below 0.4V. Where VD is the forward voltage drop of the catch diode 10000 (~0.4V) and VSW is the voltage drop of the internal switch (~0.67V at maximum load). This leads to a minimum input 1000 voltage of: 100 V V OUT + VD IN(MIN)= – VD + VSW (µA) I Q DCMAX 10 DCMAX can be adjusted with frequency. 1 The boost capacitor is charged with the energy stored in 0.1 the inductor, the circuit will rely on some minimum load 0 1 2 3 4 5 6 7 8 current to sustain the charge across the boost capacitor. EN/UVLO (V) 3686 F01
Figure 1. IQ vs VEN/UVLO (VIN = 10V)
3686fc 10 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Typical Performance Characteristics Pin Functions Block Diagram Operation Applications Information Typical Applications Package Description Revision History Related Parts
ApplicAtions inForMAtion FB Resistor Network
45 The output voltage is programmed with a resistor divider 40 between the output and the FB pin. Choose the 1% resis- 35 tors according to: 30 25 ⎛ V R1 OUT ⎞ 20 = R2 – 1 EN/UVLO (µA) ⎝⎜ 0.8V ⎠⎟ 15 10 R2 should be 20k or less to avoid bias current errors. 5 Reference designators refer to the Block Diagram. 0 0 10 20 30 40 50
Programmable Undervoltage Lockout
EN/UVLO (V) 3686 F02 The EN/UVLO pin can be programmed by an external re-
Figure 2. EN/UVLO Pin Current
sistor divider between VIN and the EN/UVLO pin. Choose the resistors according to:
Input Voltage Range
V The input voltage range for the LT3686 applications depends R4=R5 IN – 1 on the output voltage and on the absolute maximum ratings 1.27V of the VIN and BOOST pins. The minimum input voltage R4 also sets the hysteresis voltage for the programmable is determined by either the LT3686’s minimum operating UVLO: voltage of 3.6V, or by its maximum duty cycle. Hysteresis = R4 • 2.4µA The duty cycle is the fraction of time that the internal switch is on and is determined by the input and output voltages: Once VIN drops below the programmed voltage, the LT3686 will enter a low quiescent current state (I V Q ≈ 15µA). To DC= OUT + VD shutdown the LT3686 completely (IQ < 1µA), reduce EN/ VIN – VSW + VD UVLO pin voltage to below 0.4V. Where VD is the forward voltage drop of the catch diode 10000 (~0.4V) and VSW is the voltage drop of the internal switch (~0.67V at maximum load). This leads to a minimum input 1000 voltage of: 100 V V OUT + VD IN(MIN)= – VD + VSW (µA) I Q DCMAX 10 DCMAX can be adjusted with frequency. 1 The boost capacitor is charged with the energy stored in 0.1 the inductor, the circuit will rely on some minimum load 0 1 2 3 4 5 6 7 8 current to sustain the charge across the boost capacitor. EN/UVLO (V) 3686 F01
Figure 1. IQ vs VEN/UVLO (VIN = 10V)
3686fc 10 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Typical Performance Characteristics Pin Functions Block Diagram Operation Applications Information Typical Applications Package Description Revision History Related Parts