Datasheet LT3686A (Analog Devices) - 10
| Hersteller | Analog Devices |
| Beschreibung | 37V/1.2A Step-Down Regulator in 3mm × 3mm DFN and MSE |
| Seiten / Seite | 30 / 10 — ApplicAtions inForMAtion. FB Resistor Network. Programmable Undervoltage … |
| Dateiformat / Größe | PDF / 522 Kb |
| Dokumentensprache | Englisch |
ApplicAtions inForMAtion. FB Resistor Network. Programmable Undervoltage Lockout. Figure 2. EN/UVLO Pin Current
Modelllinie für dieses Datenblatt
Textversion des Dokuments
LT3686A
ApplicAtions inForMAtion FB Resistor Network
45 The output voltage is programmed with a resistor divider 40 between the output and the FB pin. Choose the 1% resis- 35 tors according to: 30 25 ⎛ V R1 OUT ⎞ = R2 – 1 20 ⎝⎜ 0.8V ⎠⎟ EN/UVLO (µA) 15 10 R2 should be 20k or less to avoid bias current errors. 5 Reference designators refer to the Block Diagram. 0 0 10 20 30 40 50
Programmable Undervoltage Lockout
EN/UVLO (V) 3686A F02 The EN/UVLO pin can be programmed by an external re-
Figure 2. EN/UVLO Pin Current
sistor divider between VIN and the EN/UVLO pin. Choose the resistors according to:
Input Voltage Range
The input voltage range for the LT3686A applications V R4 = R5 IN – 1 depends on the output voltage and on the absolute maxi- 1.28V mum ratings of the VIN and BOOST pins. The minimum input voltage is determined by either the LT3686A’s R4 also sets the hysteresis voltage for the programmable minimum operating voltage of 3.6V, or by its maximum UVLO: duty cycle. Hysteresis = R4 • 2.4µA The duty cycle is the fraction of time that the internal Once VIN drops below the programmed voltage, the switch is on and is determined by the input and output LT3686A will enter a low quiescent current state (Iq ≈ voltages: 15µA). To shutdown the LT3686A completely (Iq < 1µA), V reduce EN/UVLO pin voltage to below 0.4V. DC= OUT + VD VIN – VSW + VD 10000 Where VD is the forward voltage drop of the catch diode 1000 (~0.4V) and VSW is the voltage drop of the internal switch (~0.67V at maximum load). This leads to a minimum input 100 voltage of: (µA) I Q V 10 V OUT + VD IN(MIN) = – VD + VSW DCMAX 1 DCMAX can be adjusted with frequency. 0.1 0 1 2 3 4 5 6 7 8 The boost capacitor is charged with the energy stored in the EN/UVLO (V) inductor, the circuit wil rely on some minimum load current 3686A F01 to sustain the charge across the boost capacitor.
Figure 1. IQ vs VEN/UVLO (VIN = 10V)
3686afa 10 Document Outline Features Description Applications Typical Application Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Typical Performance Characteristics Pin Functions Block Diagram Operation Applications Information Typical Applications Package Description Revision History Typical Application Related Parts
ApplicAtions inForMAtion FB Resistor Network
45 The output voltage is programmed with a resistor divider 40 between the output and the FB pin. Choose the 1% resis- 35 tors according to: 30 25 ⎛ V R1 OUT ⎞ = R2 – 1 20 ⎝⎜ 0.8V ⎠⎟ EN/UVLO (µA) 15 10 R2 should be 20k or less to avoid bias current errors. 5 Reference designators refer to the Block Diagram. 0 0 10 20 30 40 50
Programmable Undervoltage Lockout
EN/UVLO (V) 3686A F02 The EN/UVLO pin can be programmed by an external re-
Figure 2. EN/UVLO Pin Current
sistor divider between VIN and the EN/UVLO pin. Choose the resistors according to:
Input Voltage Range
The input voltage range for the LT3686A applications V R4 = R5 IN – 1 depends on the output voltage and on the absolute maxi- 1.28V mum ratings of the VIN and BOOST pins. The minimum input voltage is determined by either the LT3686A’s R4 also sets the hysteresis voltage for the programmable minimum operating voltage of 3.6V, or by its maximum UVLO: duty cycle. Hysteresis = R4 • 2.4µA The duty cycle is the fraction of time that the internal Once VIN drops below the programmed voltage, the switch is on and is determined by the input and output LT3686A will enter a low quiescent current state (Iq ≈ voltages: 15µA). To shutdown the LT3686A completely (Iq < 1µA), V reduce EN/UVLO pin voltage to below 0.4V. DC= OUT + VD VIN – VSW + VD 10000 Where VD is the forward voltage drop of the catch diode 1000 (~0.4V) and VSW is the voltage drop of the internal switch (~0.67V at maximum load). This leads to a minimum input 100 voltage of: (µA) I Q V 10 V OUT + VD IN(MIN) = – VD + VSW DCMAX 1 DCMAX can be adjusted with frequency. 0.1 0 1 2 3 4 5 6 7 8 The boost capacitor is charged with the energy stored in the EN/UVLO (V) inductor, the circuit wil rely on some minimum load current 3686A F01 to sustain the charge across the boost capacitor.
Figure 1. IQ vs VEN/UVLO (VIN = 10V)
3686afa 10 Document Outline Features Description Applications Typical Application Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Typical Performance Characteristics Pin Functions Block Diagram Operation Applications Information Typical Applications Package Description Revision History Typical Application Related Parts