Datasheet ADP5043 (Analog Devices) - 4

ADP5043 Data Sheet Parameter Min Typ Max Unit Test Conditions/Comments
Watchdog 2 Timeout Period (tWD2) Option A 6 7.5 9 sec Option B Watchdog 2 disabled Option C 3.2 4 4.8 min Option D 6.4 8 9.6 min Option E 11.2 16 19.2 min Option F 25.6 32 38.4 min Option G 51.2 64 76.8 min Option H 102.4 128 153.8 min Watchdog 2 Power Off Period (tPOFF) Option A 210 ms Option B 400 ms WDI1 Pulse Width 80 ns VIL = 0.4 V, VIH = 1.2 V WDI2 Pulse Width 8 µs VIL = 0.4 V, VIH = 1.2 V Watchdog Status Timeout Period (tWDCLEAR) 11.2 sec WDI1 Input Current (Source) 8 15 20 µA VWDI1 = VCC, time average WDI1 Input Current (Sink) −30 −25 −14 µA VWDI1 = 0, time average WDI2 Internal Pull-Down 45 kΩ MANUAL RESET INPUT MR Input Pulse Width 1 µs MR Glitch Rejection 220 ns MR Pull-Up Resistance 25 52 80 kΩ MR to Reset Delay 280 ns VCC = 5 V Rev. B | Page 4 of 30 Document Outline FEATURES GENERAL DESCRIPTION HIGH LEVEL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS GENERAL SPECIFICATIONS SUPERVISORY SPECIFICATIONS BUCK SPECIFICATIONS LDO SPECIFICATIONS INPUT AND OUTPUT CAPACITOR, RECOMMENDED SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL DATA THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION POWER MANAGEMENT UNIT Thermal Protection Undervoltage Lockout Enable/Shutdown BUCK SECTION Control Scheme PWM Mode Power Save Mode (PSM) PSM Current Threshold Short-Circuit Protection Soft Start Current Limit 100% Duty Operation LDO SECTION SUPERVISORY SECTION Reset Output Manual Reset Input Watchdog 1 Input Watchdog 2 Input Watchdog Status Indicator APPLICATIONS INFORMATION BUCK EXTERNAL COMPONENT SELECTION Inductor Output Capacitor Input Capacitor LDO CAPACITOR SELECTION Output Capacitor Input Bypass Capacitor Input and Output Capacitor Properties SUPERVISORY SECTION Watchdog 1 Input Current Negative-Going VCC Transients Watchdog Software Considerations PCB LAYOUT GUIDELINES POWER DISSIPATION/THERMAL CONSIDERATIONS Buck Regulator Power Dissipation LDO Regulator Power Dissipation Junction Temperature EVALUATION BOARD SCHEMATICS AND ARTWORK SUGGESTED LAYOUT BILL OF MATERIALS APPLICATION DIAGRAM FACTORY PROGRAMMABLE OPTIONS OUTLINE DIMENSIONS ORDERING GUIDE