Datasheet ADP2127 (Analog Devices) - 5

HerstellerAnalog Devices
BeschreibungUltralow Profile, 500 mA, 6 MHz, Synchronous, Step-Down, DC-to-DC, EWLP
Seiten / Seite20 / 5 — Data Sheet. ADP2126/ADP2127. ABSOLUTE MAXIMUM RATINGS Table 2. Parameter …
RevisionB
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DokumentenspracheEnglisch

Data Sheet. ADP2126/ADP2127. ABSOLUTE MAXIMUM RATINGS Table 2. Parameter Rating. THERMAL RESISTANCE. THERMAL CONSIDERATIONS

Data Sheet ADP2126/ADP2127 ABSOLUTE MAXIMUM RATINGS Table 2 Parameter Rating THERMAL RESISTANCE THERMAL CONSIDERATIONS

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Data Sheet ADP2126/ADP2127 ABSOLUTE MAXIMUM RATINGS Table 2.
ambient temperature can exceed the maximum limit as long as the junction temperature is within specification limits.
Parameter Rating
VIN to GND −0.3 V to +6 V The operating junction temperature (TJ) of the device is dependent EXTCLK to GND −0.3 V to +6 V on the ambient temperature (TA), the power dissipation of the SW, MODE to GND −0.3 V to VIN device (PD), and the junction-to-ambient thermal resistance of FB to GND −0.3 V to +3.6 V the package (θJA). TJ is calculated using the following formula: Operating Ambient Temperature (TA) –40°C to +85°C1 TJ = TA + (PD × θJA) (1) Operating Junction Temperature (TJ) –40°C to +125°C at I See the Applications Information section for further information LOAD = 500 mA Soldering Conditions JEDEC J-STD-020 on calculating the operating junction temperature for a specific application. 1 The maximum operating junction temperature (TJ (MAX)) supersedes the
THERMAL RESISTANCE
maximum operating ambient temperature (TA (MAX)). See the Thermal Considerations section for more information. θJA of the package is based on modeling and calculation using a Stresses above those listed under Absolute Maximum Ratings 4-layer board. θJA is highly dependent on the application and may cause permanent damage to the device. This is a stress board layout. In applications where high maximum power rating only; functional operation of the device at these or any dissipation exists, attention to thermal board design is required. other conditions above those indicated in the operational The value of θJA may vary, depending on PCB material, layout, section of this specification is not implied. Exposure to absolute and environmental conditions. maximum rating conditions for extended periods may affect θJA is specified for worst-case conditions, that is, a device soldered device reliability. on a circuit board for surface-mount packages. θJA is determined Absolute maximum ratings apply individually only, not in according to JEDEC Standard JESD51-9 on a 4-layer printed combination. circuit board (PCB).
THERMAL CONSIDERATIONS Table 3. Thermal Resistance (4-Layer PCB)
The maximum operating junction temperature (TJ (MAX))
Package Type θJA Unit
supersedes the maximum operating ambient temperature 6-Ball Bumped Bare Die Sales 105 °C/W (TA (MAX)) because the ADP2126/ADP2127 may be damaged 6-Pad Embedded Wafer Level Package 105 °C/W when the junction temperature limits are exceeded. Monitoring ambient temperature does not guarantee that TJ is within the specified temperature limits.
ESD CAUTION
In applications with high power dissipation and poor PCB thermal resistance, the maximum ambient temperature may need to be derated. In applications with moderate power dissipation and good PCB thermal resistance, the maximum Rev. B | Page 5 of 20 Document Outline FEATURES APPLICATIONS TYPICAL APPLICATIONS CIRCUIT GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING DIAGRAMS ABSOLUTE MAXIMUM RATINGS THERMAL CONSIDERATIONS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION OVERVIEW EXTERNAL CLOCK (EXTCLK) ENABLE SPREAD SPECTRUM OSCILLATOR MODE SELECTION Pulse-Width Modulation (PWM) Mode Auto Mode (PFM and PWM Switching) Pulse Frequency Modulation (PFM) Mode Mode Transition INTERNAL CONTROL FEATURES Synchronous Rectification Soft Start PROTECTION FEATURES Overcurrent Protection Output Short-Circuit Protection (SCP) Thermal Shutdown (TSD) Protection Undervoltage Lockout (UVLO) TIMING CONSTRAINTS Shutdown Time Power-Off Time APPLICATIONS INFORMATION INDUCTOR SELECTION INPUT CAPACITOR SELECTION OUTPUT CAPACITOR SELECTION THERMAL CONSIDERATIONS PCB LAYOUT GUIDELINES OUTLINE DIMENSIONS ORDERING GUIDE