Datasheet ADP5024 (Analog Devices)

Dual 3 MHz, 1200 mA Buck Regulators with One 300 mA LDO Data Sheet ADP5024 FEATURES
a predefined threshold. When the load current falls below a pre-
Main input voltage range: 2.3 V to 5.5 V
defined threshold, the regulator operates in power save mode
Two 1200 mA buck regulators and one 300 mA LDO
(PSM), improving the light load efficiency.
24-lead, 4 mm × 4 mm LFCSP package Table 1. Family Models Regulator accuracy: ±1.8% Maximum Factory programmable or external adjustable VOUTx Model Channels Current Package 3 MHz buck operation with forced PWM and automatic
ADP5023 2 Buck, 1 LDO 800 mA, LFCSP (CP-24-10)
PWM/PSM modes
300 mA
BUCK1/BUCK2: output voltage range from 0.8 V to 3.8 V
ADP5024 2 Buck, 1 LDO 1.2 A, LFCSP (CP-24-10) 300 mA
LDO: output voltage range from 0.8 V to 5.2 V
ADP5034 2 Buck, 2 LDOs 1.2 A, LFCSP (CP-24-10),
LDO: input supply voltage from 1.7 V to 5.5 V
300 mA TSSOP (RE-28-1)
LDO: high PSRR and low output noise
ADP5037 2 Buck, 2 LDOs 800 mA, LFCSP (CP-24-10) 300 mA
APPLICATIONS
ADP5033 2 Buck, 2 LDOs 800 mA, WLCSP (CB-16-8)
Power for processors, ASICS, FPGAs, and RF chipsets
with 2 EN pins 300 mA
Portable instrumentation and medical devices
The two bucks operate out of phase to reduce the input capacitor
Space constrained devices
requirement. The low quiescent current, low dropout voltage, and
GENERAL DESCRIPTION
wide input voltage range of the LDO extends the battery life of portable devices. The ADP5024 LDO maintains power supply The ADP5024 combines two high performance buck regula- rejection greater than 60 dB for frequencies as high as 10 kHz tors and one low dropout (LDO) regulator in a small, 24-lead, while operating with a low headroom voltage. 4 mm × 4 mm LFCSP to meet demanding performance and board space requirements. Regulators in the ADP5024 are activated though dedicated enable pins. The default output voltages can be either external y The high switching frequency of the buck regulators enables tiny set in the adjustable version or factory programmable to a wide multilayer external components and minimizes the board space. range of preset values in the fixed voltage version. When the MODE pin is set high, the buck regulators operate in forced PWM mode. When the MODE pin is set low, the buck regulators operate in PWM mode when the load current is above
TYPICAL APPLICATION CIRCUIT AVIN HOUSEKEEPING CAVIN VOUT1 0.1µF L1 1µH VIN1 2.3V TO SW1 VOUT1 AT 5.5V C1 1200mA FB1 R1 4.7µF BUCK1 C5 R2 10µF ON EN1 PGND1 EN1 OFF MODE PWM MODE PSM/PWM VOUT2 VIN2 MODE L2 1µH C2 SW2 VOUT2 AT 4.7µF 1200mA BUCK2 FB2 R3 C6 EN2 EN2 R4 PGND2 10µF ON OFF EN3 VOUT3 VOUT3 AT EN3 LDO 300mA VIN3 R5 1.7V TO (ANALOG) FB3 C7 5.5V C3 R6 1µF 1µF ADP5024
001
AGND
09888- Figure 1.
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Document Outline Features Applications General Description Typical Application Circuit Revision History Specifications General Specifications BUCK1 and BUCK2 Specifications LDO Specifications Input and Output Capacitor, Recommended Specifications Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Theory of Operation Power Management Unit Thermal Protection Undervoltage Lockout Enable/Shutdown BUCK1 and BUCK2 Control Scheme PWM Mode Power Save Mode (PSM) PSM Current Threshold Oscillator/Phasing of Inductor Switching Short-Circuit Protection Soft Start Current Limit 100% Duty Operation Active Pull-Down Resistors LDO Applications Information Buck External Component Selection Feedback Resistors Inductor Output Capacitor Input Capacitor LDO External Component Selection Feedback Resistors Output Capacitor Input Bypass Capacitor Input and Output Capacitor Properties Power Dissipation and Thermal Considerations Buck Regulator Power Dissipation LDO Regulator Power Dissipation Junction Temperature PCB Layout Guidelines Typical Application Schematics Bill of Materials Outline Dimensions Ordering Guide