Datasheet ADP5050 (Analog Devices) - 7

Data Sheet ADP5050 Parameter Symbol Min Typ Max Unit Test Conditions/Comments
CHANNEL 2 SYNC BUCK REGULATOR FB2 Pin Fixed Output Options VOUT2 3.3 5.0 V Fuse trim or I2C interface (3-bit value) Adjustable Feedback Voltage VFB2 0.800 V Feedback Voltage Accuracy VFB2(DEFAULT) −0.55 +0.55 % TJ = 25°C −1.25 +1.0 % 0°C ≤ TJ ≤ 85°C −1.5 +1.5 % −40°C ≤ TJ ≤ +125°C Feedback Bias Current IFB2 0.1 µA Adjustable voltage SW2 Pin High-Side Power FET RDSON(2H) 110 mΩ Pin-to-pin measurement On Resistance Current-Limit Threshold ITH(ILIM2) 3.50 4.4 5.28 A RILIM2 = floating 1.91 2.63 3.08 A RILIM2 = 47 kΩ 4.95 6.44 7.48 A RILIM2 = 22 kΩ Minimum On Time tMIN_ON2 117 155 ns fSW = 250 kHz to 1.4 MHz Minimum Off Time tMIN_OFF2 1/9 × tSW ns fSW = 250 kHz to 1.4 MHz Low-Side Driver, DL2 Pin Rising Time tRISING2 20 ns CISS = 1.2 nF Falling Time tFALLING2 3.4 ns CISS = 1.2 nF Sourcing Resistor tSOURCING2 10 Ω Sinking Resistor tSINKING2 0.95 Ω Error Amplifier (EA), COMP2 Pin EA Transconductance gm2 310 470 620 µS Soft Start Soft Start Time tSS2 2.0 ms SS12 connected to VREG Programmable Soft Start Range 2.0 8.0 ms Hiccup Time tHICCUP2 7 × tSS2 ms COUT Discharge Switch On Resistance RDIS2 250 Ω CHANNEL 3 SYNC BUCK REGULATOR FB3 Pin Fixed Output Options VOUT3 1.20 1.80 V Fuse trim or I2C interface (3-bit value) Adjustable Feedback Voltage VFB3 0.800 V Feedback Voltage Accuracy VFB3(DEFAULT) −0.55 +0.55 % TJ = 25°C −1.25 +1.0 % 0°C ≤ TJ ≤ 85°C −1.5 +1.5 % −40°C ≤ TJ ≤ +125°C Feedback Bias Current IFB3 0.1 µA Adjustable voltage SW3 Pin High-Side Power FET RDSON(3H) 225 mΩ Pin-to-pin measurement On Resistance Low-Side Power FET RDSON(3L) 150 mΩ Pin-to-pin measurement On Resistance Current-Limit Threshold ITH(ILIM3) 1.7 2.2 2.55 A Minimum On Time tMIN_ON3 90 120 ns fSW = 250 kHz to 1.4 MHz Minimum Off Time tMIN_OFF3 1/9 × tSW ns fSW = 250 kHz to 1.4 MHz Error Amplifier (EA), COMP3 Pin EA Transconductance gm3 310 470 620 µS Soft Start Soft Start Time tSS3 2.0 ms SS34 connected to VREG Programmable Soft Start Range 2.0 8.0 ms Hiccup Time tHICCUP3 7 × tSS3 ms COUT Discharge Switch On Resistance RDIS3 250 Ω Rev. C | Page 7 of 55 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION TYPICAL APPLICATION CIRCUIT REVISION HISTORY DETAILED FUNCTIONAL BLOCK DIAGRAM SPECIFICATIONS BUCK REGULATOR SPECIFICATIONS LDO REGULATOR SPECIFICATIONS I2C INTERFACE TIMING SPECIFICATIONS Timing Diagram ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION BUCK REGULATOR OPERATIONAL MODES PWM Mode PSM Mode Forced PWM and Automatic PWM/PSM Modes ADJUSTABLE AND FIXED OUTPUT VOLTAGES DYNAMIC VOLTAGE SCALING (DVS) INTERNAL REGULATORS (VREG AND VDD) SEPARATE SUPPLY APPLICATIONS LOW-SIDE DEVICE SELECTION BOOTSTRAP CIRCUITRY ACTIVE OUTPUT DISCHARGE SWITCH PRECISION ENABLING OSCILLATOR Phase Shift SYNCHRONIZATION INPUT/OUTPUT SOFT START PARALLEL OPERATION STARTUP WITH PRECHARGED OUTPUT CURRENT-LIMIT PROTECTION FREQUENCY FOLDBACK Pulse Skip Mode Under Maximum Duty Cycle HICCUP PROTECTION LATCH-OFF PROTECTION Short-Circuit Latch-Off Mode Overvoltage Latch-Off Mode UNDERVOLTAGE LOCKOUT (UVLO) POWER-GOOD FUNCTION INTERRUPT FUNCTION THERMAL SHUTDOWN OVERHEAT DETECTION LOW INPUT VOLTAGE DETECTION LDO REGULATOR I2C INTERFACE SDA AND SCL PINS I2C ADDRESSES SELF-CLEAR REGISTER BITS I2C INTERFACE TIMING DIAGRAMS APPLICATIONS INFORMATION ADIsimPower DESIGN TOOL PROGRAMMING THE ADJUSTABLE OUTPUT VOLTAGE VOLTAGE CONVERSION LIMITATIONS CURRENT-LIMIT SETTING SOFT START SETTING INDUCTOR SELECTION OUTPUT CAPACITOR SELECTION INPUT CAPACITOR SELECTION LOW-SIDE POWER DEVICE SELECTION PROGRAMMING THE UVLO INPUT COMPENSATION COMPONENTS DESIGN POWER DISSIPATION Buck Regulator Power Dissipation Power Switch Conduction Loss (PCOND) Switching Loss (PSW) Transition Loss (PTRAN) Thermal Shutdown LDO Regulator Power Dissipation JUNCTION TEMPERATURE DESIGN EXAMPLE SETTING THE SWITCHING FREQUENCY SETTING THE OUTPUT VOLTAGE SETTING THE CURRENT LIMIT SELECTING THE INDUCTOR SELECTING THE OUTPUT CAPACITOR SELECTING THE LOW-SIDE MOSFET DESIGNING THE COMPENSATION NETWORK SELECTING THE SOFT START TIME SELECTING THE INPUT CAPACITOR RECOMMENDED EXTERNAL COMPONENTS CIRCUIT BOARD LAYOUT RECOMMENDATIONS TYPICAL APPLICATION CIRCUITS REGISTER MAP DETAILED REGISTER DESCRIPTIONS REGISTER 1: PCTRL (CHANNEL ENABLE CONTROL), ADDRESS 0x01 REGISTER 2: VID1 (VID SETTING FOR CHANNEL 1), ADDRESS 0x02 REGISTER 3: VID23 (VID SETTING FOR CHANNEL 2 AND CHANNEL 3), ADDRESS 0x03 REGISTER 4: VID4 (VID SETTING FOR CHANNEL 4), ADDRESS 0x04 REGISTER 5: DVS_CFG (DVS CONFIGURATION FOR CHANNEL 1 AND CHANNEL 4), ADDRESS 0x05 REGISTER 6: OPT_CFG (FPWM/PSM MODE AND OUTPUT DISCHARGE FUNCTION CONFIGURATION), ADDRESS 0x06 REGISTER 7: LCH_CFG (SHORT-CIRCUIT LATCH-OFF AND OVERVOLTAGE LATCH-OFF CONFIGURATION), ADDRESS 0x07 REGISTER 8: SW_CFG (SWITCHING FREQUENCY AND PHASE SHIFT CONFIGURATION), ADDRESS 0x08 REGISTER 9: TH_CFG (TEMPERATURE WARNING AND LOW VIN WARNING THRESHOLD CONFIGURATION), ADDRESS 0x09 REGISTER 10: HICCUP_CFG (HICCUP CONFIGURATION), ADDRESS 0x0A REGISTER 11: PWRGD_MASK (CHANNEL MASK CONFIGURATION FOR PWRGD PIN), ADDRESS 0x0B REGISTER 12: LCH_STATUS (LATCH-OFF STATUS READBACK), ADDRESS 0x0C REGISTER 13: STATUS_RD (STATUS READBACK), ADDRESS 0x0D REGISTER 14: INT_STATUS (INTERRUPT STATUS READBACK), ADDRESS 0x0E REGISTER 15: INT_MASK (INTERRUPT MASK CONFIGURATION), ADDRESS 0x0F REGISTER 17: DEFAULT_SET (DEFAULT RESET), ADDRESS 0x11 FACTORY DEFAULT OPTIONS OUTLINE DIMENSIONS ORDERING GUIDE