Datasheet ADP5051 (Analog Devices) - 8

ADP5051 Data Sheet Parameter Symbol Min Typ Max Unit Test Conditions/Comments
Soft Start Soft Start Time tSS3 2.0 ms SS34 connected to VREG Programmable Soft Start Range 2.0 8.0 ms Hiccup Time tHICCUP3 7 × tSS3 ms COUT Discharge Switch On Resistance RDIS3 250 Ω CHANNEL 4 SYNC BUCK REGULATOR FB4 Pin Fixed Output Options VOUT4 2.5 5.5 V Fuse trim or I2C interface (5-bit value) Adjustable Feedback Voltage VFB4 0.800 V Feedback Voltage Accuracy VFB4(DEFAULT) −0.55 +0.55 % TJ = 25°C −1.25 +1.0 % 0°C ≤ TJ ≤ 85°C −1.5 +1.5 % −40°C ≤ TJ ≤ +125°C Feedback Bias Current IFB4 0.1 µA Adjustable voltage SW4 Pin High-Side Power FET On Resistance RDSON(4H) 225 mΩ Pin-to-pin measurement Low-Side Power FET On Resistance RDSON(4L) 150 mΩ Pin-to-pin measurement Current-Limit Threshold ITH(ILIM4) 1.7 2.2 2.55 A Minimum On Time tMIN_ON4 90 120 ns fSW = 250 kHz to 1.4 MHz Minimum Off Time tMIN_OFF4 1/9 × tSW ns fSW = 250 kHz to 1.4 MHz Error Amplifier (EA), COMP4 Pin EA Transconductance gm4 310 470 620 µS Soft Start Soft Start Time tSS4 2.0 ms SS34 connected to VREG Programmable Soft Start Range 2.0 8.0 ms Hiccup Time tHICCUP4 7 × tSS4 ms COUT Discharge Switch On Resistance RDIS4 250 Ω
SUPERVISORY SPECIFICATIONS
VIN = 12 V, VVREG = 5.1 V, TJ = −40°C to +125°C for minimum and maximum specifications, and TA = 25°C for typical specifications, unless otherwise noted.
Table 4. Parameter Symbol Min Typ Max Unit Test Conditions/Comments
THRESHOLD VOLTAGE VTH 0.494 0.500 0.505 V RESET TIMEOUT PERIOD tRP Option 0 1.05 1.4 1.97 ms Option 1 21 28 38 ms Option 2 160 200 260 ms Option 3 1.15 1.6 2.17 sec VCC TO RESET DELAY tRD 80 µs VTH falling at 1 mV/µs WATCHDOG INPUT Watchdog Timeout Period tWD Option 0 4.8 6.3 8 ms Option 1 79 102 135 ms Option 2 1.14 1.6 2.15 sec Option 3 25.6 sec WDI Pulse Width 80 ns WDI Input Threshold 0.4 1.2 V WDI Input Current (Source) 8.5 14 18.5 µA VWDI = VCC, time average WDI Input Current (Sink) −15 −22 −30 µA VWDI = 0 V, time average Rev. B | Page 8 of 55 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION TYPICAL APPLICATION CIRCUIT REVISION HISTORY FUNCTIONAL BLOCK DIAGRAM SPECIFICATIONS BUCK REGULATOR SPECIFICATIONS SUPERVISORY SPECIFICATIONS I2C INTERFACE TIMING SPECIFICATIONS Timing Diagram ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION BUCK REGULATOR OPERATIONAL MODES Pulse-Width Modulation (PWM) Mode Power Save Mode (PSM) Forced PWM and Automatic PWM/PSM Modes ADJUSTABLE AND FIXED OUTPUT VOLTAGES DYNAMIC VOLTAGE SCALING (DVS) INTERNAL REGULATORS (VREG AND VDD) SEPARATE SUPPLY APPLICATIONS LOW-SIDE DEVICE SELECTION BOOTSTRAP CIRCUITRY ACTIVE OUTPUT DISCHARGE SWITCH PRECISION ENABLING OSCILLATOR Phase Shift SYNCHRONIZATION INPUT/OUTPUT SOFT START PARALLEL OPERATION STARTUP WITH PRECHARGED OUTPUT CURRENT-LIMIT PROTECTION FREQUENCY FOLDBACK Pulse Skip Mode Under Maximum Duty Cycle HICCUP PROTECTION LATCH-OFF PROTECTION Short-Circuit Latch-Off Mode Overvoltage Latch-Off Mode UNDERVOLTAGE LOCKOUT (UVLO) POWER-GOOD FUNCTION INTERRUPT FUNCTION THERMAL SHUTDOWN OVERHEAT DETECTION LOW INPUT VOLTAGE DETECTION SUPERVISORY CIRCUIT Reset Output Watchdog Input Manual Reset Input Processor Manual Reset Mode Power On/Off Switch Mode I2C INTERFACE SDA AND SCL PINS I2C ADDRESSES SELF-CLEAR REGISTER BITS I2C INTERFACE TIMING DIAGRAMS APPLICATIONS INFORMATION ADIsimPower DESIGN TOOL PROGRAMMING THE ADJUSTABLE OUTPUT VOLTAGE VOLTAGE CONVERSION LIMITATIONS CURRENT-LIMIT SETTING SOFT START SETTING INDUCTOR SELECTION OUTPUT CAPACITOR SELECTION INPUT CAPACITOR SELECTION LOW-SIDE POWER DEVICE SELECTION PROGRAMMING THE UVLO INPUT COMPENSATION COMPONENTS DESIGN POWER DISSIPATION Buck Regulator Power Dissipation Power Switch Conduction Loss (PCOND) Switching Loss (PSW) Transition Loss (PTRAN) Thermal Shutdown JUNCTION TEMPERATURE DESIGN EXAMPLE SETTING THE SWITCHING FREQUENCY SETTING THE OUTPUT VOLTAGE SETTING THE CURRENT LIMIT SELECTING THE INDUCTOR SELECTING THE OUTPUT CAPACITOR SELECTING THE LOW-SIDE MOSFET DESIGNING THE COMPENSATION NETWORK SELECTING THE SOFT START TIME SELECTING THE INPUT CAPACITOR RECOMMENDED EXTERNAL COMPONENTS CIRCUIT BOARD LAYOUT RECOMMENDATIONS TYPICAL APPLICATION CIRCUITS REGISTER MAP DETAILED REGISTER DESCRIPTIONS REGISTER 1: PCTRL (CHANNEL ENABLE CONTROL), ADDRESS 0x01 REGISTER 2: VID1 (VID SETTING FOR CHANNEL 1), ADDRESS 0x02 REGISTER 3: VID23 (VID SETTING FOR CHANNEL 2 AND CHANNEL 3), ADDRESS 0x03 REGISTER 4: VID4 (VID SETTING FOR CHANNEL 4), ADDRESS 0x04 REGISTER 5: DVS_CFG (DVS CONFIGURATION FOR CHANNEL 1 AND CHANNEL 4), ADDRESS 0x05 REGISTER 6: OPT_CFG (FPWM/PSM MODE AND OUTPUT DISCHARGE FUNCTION CONFIGURATION), ADDRESS 0x06 REGISTER 7: LCH_CFG (SHORT-CIRCUIT LATCH-OFF AND OVERVOLTAGE LATCH-OFF CONFIGURATION), ADDRESS 0x07 REGISTER 8: SW_CFG (SWITCHING FREQUENCY AND PHASE SHIFT CONFIGURATION), ADDRESS 0x08 REGISTER 9: TH_CFG (TEMPERATURE WARNING AND LOW VIN WARNING THRESHOLD CONFIGURATION), ADDRESS 0x09 REGISTER 10: HICCUP_CFG (HICCUP CONFIGURATION), ADDRESS 0x0A REGISTER 11: PWRGD_MASK (CHANNEL MASK CONFIGURATION FOR PWRGD PIN), ADDRESS 0x0B REGISTER 12: LCH_STATUS (LATCH-OFF STATUS READBACK), ADDRESS 0x0C REGISTER 13: STATUS_RD (STATUS READBACK), ADDRESS 0x0D REGISTER 14: INT_STATUS (INTERRUPT STATUS READBACK), ADDRESS 0x0E REGISTER 15: INT_MASK (INTERRUPT MASK CONFIGURATION), ADDRESS 0x0F REGISTER 16: FORCE_SHUT (FORCED SHUT DOWN), ADDRESS 0x10 REGISTER 17: DEFAULT_SET (DEFAULT RESET), ADDRESS 0x11 FACTORY DEFAULT OPTIONS OUTLINE DIMENSIONS ORDERING GUIDE