Datasheet ADP5080 (Analog Devices) - 9

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Data Sheet ADP5080 ABSOLUTE MAXIMUM RATINGS Table 6.
Stresses above those listed under Absolute Maximum Ratings
Parameter Rating
may cause permanent damage to the device. This is a stress VBATT to GND −0.3 V to +18 V rating only; functional operation of the device at these or any VDDIO to GND −0.3 V to +4.0 V other conditions above those indicated in the operational VISW1 to GND −0.3 V to +6.5 V section of this specification is not implied. Exposure to absolute VISW2 to GND −0.3 V to +4.0 V maximum rating conditions for extended periods may affect VREG1 to GND −0.3 V to +6.5 V device reliability. VREG2 to GND −0.3 V to +4.0 V
THERMAL RESISTANCE
EN to GND −0.3 V to +18 V θ EN34 to GND −0.3 V to +6.5 V JA is specified for worst-case conditions; that is, a device soldered in a circuit board for surface-mount packages. Note FAULT to GND −0.3 V to +4.0 V that actual θ BSTCP to PVINCP −0.3 V to +6.5 V JA depends on the application environment. BSTCP to GND −0.3 V to +23 V
Table 7. Thermal Resistance
C+ to PVINCP −0.3 V to (VVDR5 + 0.3 V)
PCB Type1 θ 2 2 JA θJB Unit
C− to PGND5 −0.3 V to (VVDR5 + 0.3 V) 1S0P 60.6 7.3 °C/W PVINx to PGNDx −0.3 V to +18 V 2S2P 26.9 4.5 °C/W VDRx to PGNDx −0.3 V to +6.5 V 1 PCB type conforms to JEDEC JESD51-9 standard. BST16, BST23, BST45 to PVINx −0.3 V to +6.5 V 2 1.25 W power dissipation with zero airflow. FB1, FB2, FB3 to GND −0.3 V to +4.0 V FB4, FB5, FB6 to GND −0.3 V to +6.5 V
ESD CAUTION
VOUT6 to PGND6 −0.3 V to +6.5 V SW1A, SW1B to PGND1 −2.0 V to +18 V SW2 to PGND2 −2.0 V to +18 V SW3 to PGND3 −2.0 V to +18 V SW4 to PGND4 −2.0 V to +18 V SW5 to PGND5 −2.0 V to +18 V SW6A to PGND6 −2.0 V to +18 V SW6B to PGND6 −0.5 V to (VVOUT6 + 2.0 V) or +6.5 V, whichever is lower PGNDx to GND −0.3 V to +0.3 V VILDO7 to GND −0.3 V to +28 V VOLDO7 to GND −0.3 V to +18 V FREQ to GND −0.3 V to (VVREG2 + 0.3 V) SYNC to GND −0.3 V to +4.0 V CLKO to GND −0.3 V to (VVREG2 + 0.3 V) SCL to GND −0.3 V to +4.0 V SDA to GND −0.3 V to +4.0 V Storage Temperature Range −65°C to +150°C Operating Ambient −25°C to +85°C Temperature Range Operating Junction −25°C to +125°C Temperature Range Rev. A | Page 9 of 64 Document Outline Features Applications Functional Block Diagram General Description Table of Contents Revision History Specifications Housekeeping Block Specifications DC-to-DC Converter Block Specifications Linear Regulator Block Specifications I2C Interface Timing Specifications Timing Diagram Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Application Circuit Theory of Operation UVLO and POR Undervoltage Lockout (UVLO) Power-On Reset (POR) Discharge Switch Keep-Alive LDO Linear Regulators LDO1 VISW1 Input Current Limit for LDO1 Discharge Switch for LDO1 LDO2 VISW2 Input Current Limit for LDO2 Discharge Switch for LDO2 DC-to-DC Converter Channels Channel 1, Channel 2, and Channel 3: Buck Regulators with Flex-Mode Architecture Selecting the Output Voltage, Channel 1 to Channel 3 Current-Limit Protection, Channel 1 to Channel 3 Discharge Switch, Channel 1 to Channel 3 Gate Scaling (Channel 1 Only) Dynamic Voltage Scaling (DVS) Function Channel 4 and Channel 5: Current Mode Buck Regulators Selecting the Output Voltage, Channel 4 and Channel 5 Current-Limit Protection, Channel 4 and Channel 5 Discharge Switch, Channel 4 and Channel 5 Channel 6: Buck or Buck Boost Regulator Buck Only Configuration Buck Boost Configuration Selecting the Output Voltage, Channel 6 Current-Limit Protection, Channel 6 Discharge Switch, Channel 6 Light Load and Other Modes of Operation for the DC-to-DC Converter Channels Slew Rate Adjustment Forced PWM (FPWM) Mode Auto DCM Auto PSM Selecting Light Load Switching Modes Switching Clock External Synchronization Mode Selecting the Internal Clock Frequency Selecting the External Resistor Phase Shifting CLKO Pin Soft Start Function Channel 7: High Voltage LDO Regulator Selecting the Output Voltage, Channel 7 Discharge Switch, Channel 7 Charge Pump Charge Pump Switching Frequency Capacitor Selection Protection Diode Using the Charge Pump as the Channel 7 Input Supply Enabling and Disabling the Output Channels Sequencer Mode Manual Mode EN Function EN34 Function Power-Good Function Fault Function Undervoltage Protection (UVP) UVP Detection Delay Channel 5 Standalone Undervoltage Detection Option Recovering from UVP Overvoltage Protection (OVP) OVP Detection Delay Recovering from OVP Applications Information Component Selection for the Buck and Buck Boost Regulators Setting the Output Voltage (Adjustable Mode Channels) Selecting the Inductor Selecting the Input Capacitor Selecting the Output Capacitor Component Selection for the LDO Regulators Selecting the Capacitors PCB Layout Recommendations Sensitive Signal Treatment Grounding External Component Placement and Signal Routing Thermal Considerations I2C Interface SDA and SCL Pins I2C Address Self-Clearing Register Bits I2C Interface Timing Diagrams Control Register Information Control Register Map CONTROL REGISTER DETAILS Register 1: DSCG (Discharge Switch Control), Address 0x01 Register 2: SFTTIM1234 (Soft Start Time for Channel 1, Channel 2, Channel 3, and Channel 4), Address 0x02 Register 3: SFTTIM567 (Soft Start Time for Channel 5, Channel 6, and Channel 7), Address 0x03 Register 4: EN_DLY12 (Enable Delay Time for Channel 1 and Channel 2), Address 0x04 Register 5: EN_DLY34 (Enable Delay Time for Channel 3 and Channel 4), Address 0x05 Register 6: EN_DLY56 (Enable Delay Time for Channel 5 and Channel 6), Address 0x06 Register 7: EN_DLY7 (Enable Delay Time for Channel 7), Address 0x07 Register 8: DIS_DLY12 (Disable Delay Time for Channel 1 and Channel 2), Address 0x08 Register 9: DIS_DLY34 (Disable Delay Time for Channel 3 and Channel 4), Address 0x09 Register 10: DIS_DLY56 (Disable Delay Time for Channel 5 and Channel 6), Address 0x0A Register 11: DIS_DLY7 (Disable Delay Time for Channel 7), Address 0x0B Register 12: VID1 (Output Voltage for Channel 1), Address 0x0C Register 13: VID23 (Output Voltage for Channel 2 and Channel 3), Address 0x0D Register 14: VID45 (Output Voltage for Channel 4 and Channel 5), Address 0x0E Register 15: VID6 (Output Voltage for Channel 6), Address 0x0F Register 16: VID7_LDO12 (Output Voltage for Channel 7, LDO1, and LDO2), Address 0x10 Register 17: DVS12 (DVS Control for Channel 1 and Channel 2), Address 0x11 Register 18: SEL_FREQ (Switching Frequency for Channel 1 to Channel 6), Address 0x12 Register 19: SEL_FREQ_CP (Charge Pump Frequency), Address 0x13 Register 20: SEL_PHASE (Switching Phase for Channel 1 to Channel 6), Address 0x14 Register 23: PROT_DLY (Undervoltage/Overvoltage Protection Delay Times), Address 0x17 Register 24: PWRG (Power-Good Status), Address 0x18 Register 25: MASK_PWRG (Power-Good Masked Channels), Address 0x19 Register 26: UVPST (Undervoltage Protection Status), Address 0x1A Register 27: OVPST (Overvoltage Protection Status), Address 0x1B Register 28: AUTO-PSM (Auto PSM or Forced PWM Mode for Channel 1 to Channel 6), Address 0x1C Register 29: SEQ_MODE (Sequencer Mode), Address 0x1D Register 30: ADJ_BST_VTH6 (Adjust Boost Kick-In Threshold and Regulation Mode for Channel 6), Address 0x1E Register 31: OPT_SR_ADJ (Slew Rate Adjustment for Channel 1 to Channel 6), Address 0x1F Register 32: DCM56_GSCAL1 (Auto DCM for Channel 5 and Channel 6, Gate Scaling for Channel 1), Address 0x20 Register 33: SEL_INP_LDO12 (Input Selection for LDO1 and LDO2), Address 0x21 Register 34: SEL_IND_UV5 (Independent UVP Control for Channel 5), Address 0x22 Register 35: OPTION_SEL (Channel 1 Output Voltage Reduction, Disable Delay Time Increase, EN34 Function), Address 0x23 Register 48: PCTRL (Channel Enable Control), Address 0x30 Factory Default Options Outline Dimensions Ordering Guide