Datasheet LTC3624, LTC3624-2 (Analog Devices) - 7
| Hersteller | Analog Devices |
| Beschreibung | 17V, 2A Synchronous Step-Down Regulator with 3.5μA Quiescent Current |
| Seiten / Seite | 20 / 7 — pin FuncTions (DFN/MSOP) SW (Pin 1/Pins 1, 2):. INTVCC (Pin 6/Pin 9):. … |
| Dateiformat / Größe | PDF / 327 Kb |
| Dokumentensprache | Englisch |
pin FuncTions (DFN/MSOP) SW (Pin 1/Pins 1, 2):. INTVCC (Pin 6/Pin 9):. VIN (Pin 2/Pins 3, 4):. MODE/SYNC (Pin 7/Pin 10):
Modelllinie für dieses Datenblatt
- LTC3624EDD#PBF LTC3624EDD#TRPBF LTC3624EDD-2#PBF LTC3624EDD-2#TRPBF LTC3624EDD-23.3#PBF LTC3624EDD-23.3#TRPBF LTC3624EDD-25#PBF LTC3624EDD-25#TRPBF LTC3624EDD-3.3#PBF LTC3624EDD-3.3#TRPBF LTC3624EDD-5#PBF LTC3624EDD-5#TRPBF LTC3624EMSE#PBF LTC3624EMSE#TRPBF LTC3624EMSE-2#PBF LTC3624EMSE-2#TRPBF LTC3624EMSE-23.3#PBF LTC3624EMSE-23.3#TRPBF LTC3624EMSE-25#PBF LTC3624EMSE-25#TRPBF LTC3624EMSE-3.3#PBF LTC3624EMSE-3.3#TRPBF LTC3624EMSE-5#PBF LTC3624EMSE-5#TRPBF LTC3624HMSE#PBF LTC3624HMSE#TRPBF LTC3624HMSE-2#PBF LTC3624HMSE-2#TRPBF LTC3624HMSE-23.3#PBF LTC3624HMSE-23.3#TRPBF LTC3624HMSE-25#PBF LTC3624HMSE-25#TRPBF LTC3624HMSE-3.3#PBF LTC3624HMSE-3.3#TRPBF LTC3624HMSE-5#PBF LTC3624HMSE-5#TRPBF LTC3624IDD#PBF LTC3624IDD#TRPBF LTC3624IDD-2#PBF LTC3624IDD-2#TRPBF LTC3624IDD-23.3#PBF LTC3624IDD-23.3#TRPBF LTC3624IDD-25#PBF LTC3624IDD-25#TRPBF LTC3624IDD-3.3#PBF LTC3624IDD-3.3#TRPBF LTC3624IDD-5#PBF LTC3624IDD-5#TRPBF LTC3624IMSE#PBF LTC3624IMSE#TRPBF LTC3624IMSE-2#PBF LTC3624IMSE-2#TRPBF LTC3624IMSE-23.3#PBF LTC3624IMSE-23.3#TRPBF LTC3624IMSE-25#PBF LTC3624IMSE-25#TRPBF LTC3624IMSE-3.3#PBF LTC3624IMSE-3.3#TRPBF LTC3624IMSE-5#PBF LTC3624IMSE-5#TRPBF
Textversion des Dokuments
LTC3624/LTC3624-2
pin FuncTions (DFN/MSOP) SW (Pin 1/Pins 1, 2):
Switch Node Connection to the
INTVCC (Pin 6/Pin 9):
Low Dropout Regulator. Bypass with Inductor of the Step-Down Regulator. at least 2.2µF to Ground.
VIN (Pin 2/Pins 3, 4):
Input Voltage of the Step-Down
MODE/SYNC (Pin 7/Pin 10):
Burst Mode Select and Ex- Regulator. ternal Clock Synchronization of the Step-Down Regulator.
RUN (Pin 3/Pin 5):
Logic Controlled RUN Input. Do not Tie MODE/SYNC to INTVCC for Burst Mode operation with leave this pin floating. Logic high activates the step-down a 800mA peak current clamp, tie MODE/SYNC to GND for regulator. pulse skipping operation, and tie MODE/SYNC to a volt- age between 1V and VINTVCC – 1.2V for forced continuous
PGOOD (Pin 4/Pin 6):
VOUT within Regulation Indicator. mode. Furthermore, connecting MODE/SYNC to an external
FB (Pin 5/Pin 8):
Feedback Input to the Error Amplifier clock will sync the system clock to the external clock and of the Step-Down Regulator. Connect a resistor divider put the part in forced continuous mode. tap to this pin. The output voltage can be adjusted from
GND (Pin 8, Exposed Pad Pin 9/Pins 11, 12, Exposed
0.6V to VIN by:
Pad Pin 13):
Power and Signal Ground. The exposed pad V must be soldered to PCB ground for electrical and rated OUT = 0.6V • [1 + (R2/R1)] thermal performance. See Figure 1.
NC (Pin 7, MSOP Only):
No Connect. There is no electrical For fixed VOUT options, connect the FB pin directly to VOUT. connection to this pin inside the package. 36242fd For more information www.linear.com/LTC3624 7 Document Outline Features Applications Typical Application Description Absolute Maximum Ratings Pin Configuration Order Information Order Information Electrical Characteristics Typical Performance Characteristics Pin Functions Block Diagram Operation Applications Information Package Description Revision History Typical Application Related Parts
pin FuncTions (DFN/MSOP) SW (Pin 1/Pins 1, 2):
Switch Node Connection to the
INTVCC (Pin 6/Pin 9):
Low Dropout Regulator. Bypass with Inductor of the Step-Down Regulator. at least 2.2µF to Ground.
VIN (Pin 2/Pins 3, 4):
Input Voltage of the Step-Down
MODE/SYNC (Pin 7/Pin 10):
Burst Mode Select and Ex- Regulator. ternal Clock Synchronization of the Step-Down Regulator.
RUN (Pin 3/Pin 5):
Logic Controlled RUN Input. Do not Tie MODE/SYNC to INTVCC for Burst Mode operation with leave this pin floating. Logic high activates the step-down a 800mA peak current clamp, tie MODE/SYNC to GND for regulator. pulse skipping operation, and tie MODE/SYNC to a volt- age between 1V and VINTVCC – 1.2V for forced continuous
PGOOD (Pin 4/Pin 6):
VOUT within Regulation Indicator. mode. Furthermore, connecting MODE/SYNC to an external
FB (Pin 5/Pin 8):
Feedback Input to the Error Amplifier clock will sync the system clock to the external clock and of the Step-Down Regulator. Connect a resistor divider put the part in forced continuous mode. tap to this pin. The output voltage can be adjusted from
GND (Pin 8, Exposed Pad Pin 9/Pins 11, 12, Exposed
0.6V to VIN by:
Pad Pin 13):
Power and Signal Ground. The exposed pad V must be soldered to PCB ground for electrical and rated OUT = 0.6V • [1 + (R2/R1)] thermal performance. See Figure 1.
NC (Pin 7, MSOP Only):
No Connect. There is no electrical For fixed VOUT options, connect the FB pin directly to VOUT. connection to this pin inside the package. 36242fd For more information www.linear.com/LTC3624 7 Document Outline Features Applications Typical Application Description Absolute Maximum Ratings Pin Configuration Order Information Order Information Electrical Characteristics Typical Performance Characteristics Pin Functions Block Diagram Operation Applications Information Package Description Revision History Typical Application Related Parts