Datasheet LTC7124 (Analog Devices) - 3

LTC7124
ELECTRICAL CHARACTERISTICS The
l
denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at TA = 25°C. VIN1 = VIN2 = 12V, unless otherwise noted. (Note 3) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
ΔVLOAD&LINE Output Voltage Load and Line Regulation VIN = 3.1 to 17V (Note 5) 0.3 0.5 % REG ITH = 0.3V to 0.9V IFB Feedback Pin Input Current 10 nA gm(EA) Error Amplifier Transconductance ITH = 0.6V 300 500 700 µS tON-MIN Minimum On Time (Note 7) 50 ns ISW Top NMOS Switch Leakage 0.1 ±1 µA Bottom NMOS Switch Leakage 0.1 ±1 µA RDS(ON) Top NMOS On Resistance 80 mΩ Bottom NMOS On Resistance 40 mΩ VRUN RUN Input High 1.0 V RUN Input Low 0.3 V RUN Input Current VRUN = 12V 0 ±100 nA VMODE/SYNC Pulse Skip Mode 0.3 V Burst Mode Operation INTVCC–0.4 V Forced Continuous Mode 1.0 INTVCC–1.2 V VILIM ILIM Input Threshold Input Low 0.2 V Input High INTVCC–0.3 V ILIM Peak Current Limit ILIM = 0V (Both Channels) 4.4 5.0 5.6 A ILIM = INTVCC (Both Channels) 2.2 2.6 3.0 A ILIM = Floating, Channel 1 4.4 5.0 5.6 A ILIM = Floating, Channel 2 2.2 2.6 3.0 A tSS Internal Soft Start Time 1100 µs VINTVCC VINTVCC LDO Output Voltage VIN1 > 4V 3.6 V VINTVCC Undervoltage Lockout VIN1 Ramping Up l 2.75 2.9 3.05 V VINTVCC Undervoltage Lockout Hysteresis 300 mV VIN Overvoltage Lockout Rising l 17.9 18.4 18.9 V VIN Overvoltage Lockout Hysteresis 500 mV fOSC RT Programmable Oscillator Frequency RRT = 100k l 0.92 1 1.08 MHz fSYNC SYNC Capture Range % of Programmed Frequency l 75 125 % Power Good Range ±5 ±7.5 ±10 % RPGOOD Power Good Resistance 650 1000 Ω tPGOOD PGOOD Delay PGOOD Low to High, RRT = 100k 25 µs PGOOD High to Low, RRT = 100k 32 µs
Note 1:
Stresses beyond those listed under Absolute Maximum Ratings TJ is calculated from the ambient TA and power dissipation PD according may cause permanent damage to the device. Exposure to any Absolute to the following formula
:
TJ = TA + (PD • θJA) Maximum Rating condition for extended periods may affect device
Note 4:
The Quiescent Current in active mode does not include switching reliability and lifetime. loss of the power FETs.
Note 2:
Transient Absolute Maximum Voltages should not be applied for
Note 5:
The LTC7124 is tested in a proprietary test mode that connects more than 4% of the switching duty cycle. VFB to the output of error amplifier.
Note 3:
The LTC7124 is tested under pulsed load conditions such that
Note 6:
The maximum VOUT is limited by the automatic boost refresh that TJ ≈ TA. The LTC7124E is guaranteed to meet specified performance from occurs in high duty cycle and dropout cases. The maximum VOUT value 0°C to 85°C. Specifications over the –40°C to 125°C operating junction listed here is guaranteed by design. temperature range are assured by design, characterization and correlation
Note 7:
The minimum on-time is determined by the speed of the top with statistical process controls. The LTC7124I is guaranteed over the switch driver and peak current comparator. The typical value listed here is full –40°C to 125°C operating junction temperature range. Note that the guaranteed by design. maximum ambient temperature consistent with these specifications is determined by specific operating conditions in conjunction with board layout, the rated package thermal impedance and other environmental factors. 7124fa For more information www.linear.com/LTC7124 3