Datasheet ADP5003 (Analog Devices) - 7

Data Sheet ADP5003 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 1 1 SYS ND1 ND1 1 1 1 N N N G G P P SW SW SW PVI PVI PVI 32 31 30 29 28 27 26 25 PGND1 1 24 AGND1 VOUT1 2 23 VREG EN1 3 22 RT ADP5003 EN2 4 21 COMP1 TOP VIEW SYNC 5 20 PWRGD (Not to Scale) PVIN2 6 19 VSET1 PVIN2 7 18 REFOUT PVIN2 8 17 VSET2 9 10 11 12 13 14 15 16 2 2 2 T T T U U U B2P B2N DO BUF ND2 F F V _L V V AG G PVO PVO PVO RE V NOTES
002
1. EXPOSED THERMAL PAD. CONNECT THE EXPOSED THERMAL PAD TO AGND1.
15021- Figure 2. Pin Configuration
Table 7. Pin Function Descriptions Pin No. Mnemonic Description
1, 31, 32 PGND1 Buck Regulator Dedicated Power Ground. 2 VOUT1 Buck Regulator Feedback Input. Connect a short sense trace to the buck output capacitor. 3 EN1 Buck Regulator Precision Enable Pin. Drive the EN1 pin high to turn on the buck regulator, and drive the EN1 pin low to turn off the buck regulator. 4 EN2 LDO Precision Enable Pin. Drive the EN2 pin high to turn on the LDO regulator, and drive the EN2 pin low to turn off the LDO regulator. 5 SYNC Synchronization Input. To synchronize the switching frequency of the device to an external clock, connect this pin to an external clock with a frequency from 300 kHz to 2.5 MHz. 6 to 8 PVIN2 LDO Regulator Power Input. Connect a 10 µF ceramic capacitor between this pin and AGND2. 9 to 11 PVOUT2 LDO Regulator Power Output. Connect a 10 µF ceramic capacitor between this pin and AGND2. 12 VFB2P LDO Regulator Positive Sense Feedback Input. Connect a sense trace to the LDO output at the load. Route this pin with the VFB2N pin on the PCB. 13 VFB2N LDO Regulator Ground Sense Feedback Input. Connect a sense trace to ground at the load. Route this pin with the VFB2P pin on the PCB. 14 VBUF Output of the LDO Reference Buffer. Connect a 0.1 µF ceramic capacitor between this pin and VFB2N. 15 AGND2 LDO Dedicated Analog Ground. 16 VREG_LDO Internal Regulator Output for the LDO. Connect a 1 µF ceramic decoupling capacitor between this pin and AGND2. Do not use this pin to power external devices. 17 VSET2 LDO Regulator Output Voltage Configuration Input. 18 REFOUT Internal Reference Output Required for Driving the External Resistor Dividers for VSET1 and VSET2. Connect a 0.22 µF ceramic capacitor between this pin and AGND2. 19 VSET1 Buck Regulator Output Voltage Configuration Input. Connect this pin to VREG to enable adaptive headroom control. 20 PWRGD Power-Good Digital Output (Open-Drain NFET Pull-Down Driver). 21 COMP1 Buck Regulator External Compensation Pin. 22 RT Resistor Adjustable Frequency Programming Input. 23 VREG Internal Regulator Output. Connect a 1 µF ceramic decoupling capacitor between this pin and AGND1. Do not use this pin to power external devices. 24 AGND1 Analog Ground. 25 PVINSYS System Power Supply for the ADP5003. Connect a 10 µF ceramic capacitor between this pin and AGND1. 26, 27 PVIN1 Buck Regulator Power Input. Connect a 10 µF ceramic capacitor between this pin and PGND1. 28 to 30 SW1 Buck Regulator Switching Output. EPAD Exposed Thermal Pad. Connect the exposed thermal pad to AGND1. Rev. 0 | Page 7 of 29 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS BUCK REGULATOR SPECIFICATIONS LDO SPECIFICATIONS ADAPTIVE HEADROOM CONTROLLER SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION POWER MANAGEMENT UNIT Adaptive Headroom Control Precision Enable/Shutdown Undervoltage Lockout (UVLO) Thermal Shutdown (TSD) Active Pull Down Soft Start (SS) Power-Good BUCK REGULATOR Control Scheme Oscillator Frequency Control External Oscillator Synchronization Buck Startup Current-Limit and Short-Circuit Protection LDO REGULATOR LDO Startup Current Limit Differential Remote Sensing POWER-GOOD OUTPUT VOLTAGE OF THE BUCK REGULATOR OUTPUT VOLTAGE OF THE LDO REGULATOR VOLTAGE CONVERSION LIMITATIONS COMPONENT SELECTION Output Capacitors Input Capacitor Inductor COMPENSATION COMPONENTS DESIGN JUNCTION TEMPERATURE BUCK REGULATOR DESIGN EXAMPLE SETTING THE SWITCHING FREQUENCY FOR THE BUCK REGULATOR SETTING THE OUTPUT VOLTAGE FOR THE BUCK REGULATOR SELECTING THE INDUCTOR FOR THE BUCK REGULATOR SELECTING THE OUTPUT CAPACITOR FOR THE BUCK REGULATOR DESIGNING THE COMPENSATION NETWORK FOR THE BUCK REGULATOR SELECTING THE INPUT CAPACITOR FOR THE BUCK REGULATOR ADAPTIVE HEADROOM CONTROL DESIGN EXAMPLE SETTING THE SWITCHING FREQUENCY FOR THE BUCK REGULATOR USING ADAPTIVE HEADROOM CONTROL SETTING THE OUTPUT VOLTAGE FOR THE BUCK REGULATOR USING ADAPTIVE HEADROOM CONTROL SELECTING THE INDUCTOR FOR THE BUCK REGULATOR USING ADAPTIVE HEADROOM CONTROL SELECTING THE OUTPUT CAPACITORS FOR THE BUCK REGULATOR USING ADAPTIVE HEADROOM CONTROL SELECTING THE INPUT CAPACITOR FOR THE BUCK REGULATOR USING ADAPTIVE HEADROOM CONTROL RECOMMENDED BUCK EXTERNAL COMPONENTS FOR THE BUCK REGULATOR BUCK CONFIGURATIONS INDEPENDENT ADAPTIVE HEADROOM LAYOUT CONSIDERATIONS OUTLINE DIMENSIONS ORDERING GUIDE