Datasheet ADP2114 (Analog Devices) - 6

HerstellerAnalog Devices
BeschreibungConfigurable, Dual 2 A/Single 4 A, Synchronous Step-Down DC-to-DC Regulator
Seiten / Seite37 / 6 — ADP2114. Data Sheet. PIN CONFIGURATION AND FUNCTION DESCRIPTIONS. 1 D. …
RevisionC
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DokumentenspracheEnglisch

ADP2114. Data Sheet. PIN CONFIGURATION AND FUNCTION DESCRIPTIONS. 1 D. SET. GOO. GND 1. 24 SW1. COMP1 2. 23 SW2. FREQ 3. 22 PGND1. SCFG 4

ADP2114 Data Sheet PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 1 D SET GOO GND 1 24 SW1 COMP1 2 23 SW2 FREQ 3 22 PGND1 SCFG 4

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ADP2114 Data Sheet PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 1 D 1 SET 1 1 1 2 3 GOO N N N FB V1 SS P EN VI VI VI 32 31 30 29 28 27 26 25 GND 1 24 SW1 COMP1 2 23 SW2 FREQ 3 22 PGND1 ADP2114 SCFG 4 21 PGND2 SYNC/CLKOUT 5 TOP VIEW 20 PGND3 (Not to Scale) OPCFG 6 19 PGND4 COMP2 7 18 SW3 VDD 8 17 SW4 9 10 11 12 13 14 15 16 2 T 2 2 2 4 5 6 E D N N N FB SS O EN VI VI VI V2S O PG NOTES
3 00
1. CONNECT THE EXPOSED THERMAL PAD
3-
TO THE SIGNAL/ANALOG GROUND PLANE.
1408 Figure 3. Pin Configuration
Table 3. Pin Function Descriptions Pin No. Mnemonic Description
1 GND Ground for the Internal Analog and Digital Circuits. Connect GND to the signal/analog ground plane before connecting to the power ground. 2 COMP1 Error Amplifier Output for Channel 1. Connect a series RC network from COMP1 to GND to compensate for Channel 1. For multiphase operation, tie COMP1 and COMP2 together. 3 FREQ Frequency Select Input. Connect this pin through a resistor to GND to set the appropriate switching frequency (see Table 5). 4 SCFG Synchronization Configuration Input. SCFG configures the SYNC/CLKOUT pin as an input or output. Tie this pin to VDD to configure SYNC/CLKOUT as an output. Tie this pin to GND to configure SYNC/CLKOUT as an input. 5 SYNC/CLKOUT This is a configurable bidirectional pin (configured with the SCFG pin—see the Pin 4 description for details). When SYNC/CLKOUT is an output, a buffered clock of twice the switching frequency with a phase shift of 90° is available on this pin. When configured as an input, this pin accepts an external clock to which the converters are synchronized. The frequency select resistor, mentioned in the description of Pin 3, must be selected close to the expected switching frequency for stable operation. 6 OPCFG Operation Configuration Input. Connect this pin through a resistor to GND to set the system mode of operation according to Table 7. This pin can be used to select a peak current limit for each power channel and enable or disable the pulse skip mode. 7 COMP2 Error Amplifier Output for Channel 2. Connect a series RC network from COMP2 to GND to compensate the Channel 2. Tie COMP1 and COMP2 together for multiphase configuration. 8 VDD Power Supply Input. The power source for the ADP2114 internal circuitry. Connect VDD and VINx with a 10 Ω resistor as close as possible to the ADP2114. Bypass VDD to GND with a 1 μF or greater capacitor. 9 FB2 Feedback Voltage Input for Channel 2. For the fixed output voltage option, connect FB2 to VOUT2. For the adjustable output voltage option, connect this pin to a resistor divider between VOUT2 and GND. The reference voltage for the adjustable output voltage option is 0.6 V. With multiphase configurations, connect FB2 to FB1 and then connect them to VOUT. 10 V2SET Output Voltage Set Pin for Channel 2. Connect this pin through a resistor to GND or tie to VDD to select a fixed output voltage option (0.8 V, 1.2 V, 1.5 V, 1.8 V, 2.5 V, or 3.3 V) or an adjust output voltage for VOUT2. See Table 4 for output voltage selection. 11 SS2 Soft Start Input for Channel 2. Place a capacitor from SS2 to GND to set the soft start period. A 10 nF capacitor sets a 1 ms soft start period. For multiphase configuration, connect SS2 to SS1. 12 PGOOD2 Open-Drain Power Good Output for Channel 2. Place a 100 kΩ pull-up resistor to VDD or any other voltage ≤ 5.5 V; PGOOD2 pulls low when Channel 2 is out of regulation. 13 EN2 Enable Input for Channel 2. Drive EN2 high to turn on the Channel 2 converter and drive EN2 low to turn off Channel 2. Tie EN2 to VDD for startup with VDD. With multiphase configuration, tie EN2 to EN1. Rev. C | Page 6 of 37 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION TYPICAL APPLICATION CIRCUIT TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS SUPPLY CURRENT LOAD TRANSIENT RESPONSE BODE PLOTS SIMPLIFIED BLOCK DIAGRAM THEORY OF OPERATION ADIsimPower DESIGN TOOL CONTROL ARCHITECTURE UNDERVOLTAGE LOCKOUT (UVLO) ENABLE/DISABLE CONTROL SOFT START POWER GOOD PULSE SKIP MODE HICCUP MODE CURRENT LIMIT THERMAL OVERLOAD PROTECTION MAXIMUM DUTY CYCLE OPERATION SYNCHRONIZATION CONVERTER CONFIGURATION SELECTING THE OUTPUT VOLTAGE SETTING THE OSCILLATOR FREQUENCY SYNCHRONIZATION AND CLKOUT OPERATION MODE CONFIGURATION EXTERNAL COMPONENTS SELECTION INPUT CAPACITOR SELECTION VDD RC FILTER INDUCTOR SELECTION OUTPUT CAPACITOR SELECTION CONTROL LOOP COMPENSATION DESIGN EXAMPLE CHANNEL 1 CONFIGURATION AND COMPONENTS SELECTION CHANNEL 2 CONFIGURATION AND COMPONENTS SELECTION SYSTEM CONFIGURATION APPLICATION CIRCUITS POWER DISSIPATION, THERMAL CONSIDERATIONS CIRCUIT BOARD LAYOUT RECOMMENDATIONS OUTLINE DIMENSIONS ORDERING GUIDE