Datasheet LT1792 (Analog Devices) - 8
| Hersteller | Analog Devices |
| Beschreibung | Low Noise, Precision, JFET Input Op Amp |
| Seiten / Seite | 12 / 8 — APPLICATI. S I FOR ATIO. Figure 2. Comparison of LT1792 and LT1007 Total … |
| Dateiformat / Größe | PDF / 183 Kb |
| Dokumentensprache | Englisch |
APPLICATI. S I FOR ATIO. Figure 2. Comparison of LT1792 and LT1007 Total Output. 1kHz Voltage Noise Versus Source Resistance
Modelllinie für dieses Datenblatt
Textversion des Dokuments
LT1792
O U U W U APPLICATI S I FOR ATIO
best bipolar op amps, with higher current noise, will 1k LT1007* eventually lose out to the LT1792 when transducer imped- z) CS LT1792* ance increases. The low voltage noise of the LT1792 √H RS allows it to surpass most single JFET op amps available. 100 – + V LT1007† For the best performance versus area available anywhere, O RS CS the LT1792 is offered in the SO-8 surface mount package with no degradation in performance. 10 LT1792† The low voltage and current noise offered by the LT1792 LT1792 INPUT NOISE VOLTAGE (nV/ LT1007 makes it useful in a wide range of applications, especially RESISTOR NOISE ONLY where high impedance, capacitive transducers are used 1 100 1k 10k 100k 1M 10M 100M such as hydrophones, precision accelerometers and photo SOURCE RESISTANCE (Ω) 1792 F02 diodes. The total output noise in such a system is the gain SOURCE RESISTANCE = 2RS = R times the RMS sum of the op amp input referred voltage * PLUS RESISTOR † PLUS RESISTOR 1000pF CAPACITOR noise, the thermal noise of the transducer, and the op amp V 2 n = AV √Vn (OP AMP) + 4kTR + 2qIB • R2 bias current noise times the transducer impedance.
Figure 2. Comparison of LT1792 and LT1007 Total Output
Figure 2 shows total input voltage noise versus source
1kHz Voltage Noise Versus Source Resistance
resistance. In a low source resistance (<5k) application the op amp voltage noise will dominate the total noise. current noise of FET input op amps. Clearly, the LT1792 This means the LT1792 will beat out any JFET op amp, only will extend the range of high impedance transducers the lowest noise bipolar op amps have the edge that can be used for high signal-to-noise ratios. This at low source resistances. As the source resistance in- makes the LT1792 the best choice for high impedance, creases from 5k to 50k, the LT1792 will match the best capacitive transducers. bipolar op amps for noise performance, since the thermal noise of the transducer (4kTR) begins to dominate the The high input impedance JFET front end makes the total noise. A further increase in source resistance, above LT1792 suitable in applications where very high charge 50k, is where the op amp’s current noise component (2qIB sensitivity is required. Figure 3 illustrates the LT1792 in its RTRANS) will eventually dominate the total noise. At these inverting and noninverting modes of operation. A charge high source resistances, the LT1792 will out perform amplifier is shown in the inverting mode example; here the the lowest noise bipolar op amp due to the inherently low gain depends on the principal of charge conservation at R2 RF CB CF RB – – R1 OUTPUT C OUTPUT + S RS + TRANSDUCER C ≅ B CS CB = CF CS C R R R S RS B = RS B = RF S RS > R1 OR R2 C dQ dV B RB Q = CV; = I = C dt dt TRANSDUCER 1792 F03
Figure 3. Noninverting and Inverting Gain Configurations
8
O U U W U APPLICATI S I FOR ATIO
best bipolar op amps, with higher current noise, will 1k LT1007* eventually lose out to the LT1792 when transducer imped- z) CS LT1792* ance increases. The low voltage noise of the LT1792 √H RS allows it to surpass most single JFET op amps available. 100 – + V LT1007† For the best performance versus area available anywhere, O RS CS the LT1792 is offered in the SO-8 surface mount package with no degradation in performance. 10 LT1792† The low voltage and current noise offered by the LT1792 LT1792 INPUT NOISE VOLTAGE (nV/ LT1007 makes it useful in a wide range of applications, especially RESISTOR NOISE ONLY where high impedance, capacitive transducers are used 1 100 1k 10k 100k 1M 10M 100M such as hydrophones, precision accelerometers and photo SOURCE RESISTANCE (Ω) 1792 F02 diodes. The total output noise in such a system is the gain SOURCE RESISTANCE = 2RS = R times the RMS sum of the op amp input referred voltage * PLUS RESISTOR † PLUS RESISTOR 1000pF CAPACITOR noise, the thermal noise of the transducer, and the op amp V 2 n = AV √Vn (OP AMP) + 4kTR + 2qIB • R2 bias current noise times the transducer impedance.
Figure 2. Comparison of LT1792 and LT1007 Total Output
Figure 2 shows total input voltage noise versus source
1kHz Voltage Noise Versus Source Resistance
resistance. In a low source resistance (<5k) application the op amp voltage noise will dominate the total noise. current noise of FET input op amps. Clearly, the LT1792 This means the LT1792 will beat out any JFET op amp, only will extend the range of high impedance transducers the lowest noise bipolar op amps have the edge that can be used for high signal-to-noise ratios. This at low source resistances. As the source resistance in- makes the LT1792 the best choice for high impedance, creases from 5k to 50k, the LT1792 will match the best capacitive transducers. bipolar op amps for noise performance, since the thermal noise of the transducer (4kTR) begins to dominate the The high input impedance JFET front end makes the total noise. A further increase in source resistance, above LT1792 suitable in applications where very high charge 50k, is where the op amp’s current noise component (2qIB sensitivity is required. Figure 3 illustrates the LT1792 in its RTRANS) will eventually dominate the total noise. At these inverting and noninverting modes of operation. A charge high source resistances, the LT1792 will out perform amplifier is shown in the inverting mode example; here the the lowest noise bipolar op amp due to the inherently low gain depends on the principal of charge conservation at R2 RF CB CF RB – – R1 OUTPUT C OUTPUT + S RS + TRANSDUCER C ≅ B CS CB = CF CS C R R R S RS B = RS B = RF S RS > R1 OR R2 C dQ dV B RB Q = CV; = I = C dt dt TRANSDUCER 1792 F03
Figure 3. Noninverting and Inverting Gain Configurations
8