Datasheet LT1672, LT1673, LT1674 (Analog Devices) - 9
| Hersteller | Analog Devices |
| Beschreibung | 2µA Max, AV ≥ 5 Single, Dual and Quad Over-The-Top Precision Rail-to-Rail Input and Output Op Amps |
| Seiten / Seite | 12 / 9 — APPLICATIO S I FOR ATIO. Output. Rail-to-Rail Operation. Figure 3. … |
| Dateiformat / Größe | PDF / 220 Kb |
| Dokumentensprache | Englisch |
APPLICATIO S I FOR ATIO. Output. Rail-to-Rail Operation. Figure 3. Simplified Schematic
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Textversion des Dokuments
LT1672/LT1673/LT1674
U U W U APPLICATIO S I FOR ATIO
The device will not be damaged if the inputs are taken lower and (VCC – 0.8V), Q1 and Q2 are active. When the input than 300mV below the negative supply as long as the cur- common mode exceeds (VCC – 0.8V), Q7 turns on, rent out of the pin is limited to less than 10mA. However, diverting the current from diff amp Q1-Q2 to current the output phase is not guaranteed and the supply current mirror Q8-Q9. The current from Q8 biases on the other will increase. diff amp consisting of PNP’s Q5-Q6 and NPN’s Q3-Q4. Though Q5-Q6 are driven from the emitters rather than
Output
the base, the basic diff amp action is the same. When the common mode voltage is between (V The graph, Capacitive Load Handling, shows amplifier sta- CC – 0.8V) and VCC, devices Q3 and Q4 act as followers, forming a buffer bility with the output biased at half supply. If the output is between the amplifier inputs and the emitters of the Q5- to be operated within about 100mV of the positive rail, the Q6. If the common mode voltage is taken above V allowable load capacitance is less. With this output volt- CC, Schottky diodes D1 and D2 reverse bias and devices Q3 age, the worst case occurs at AV = 5 and light loads, where and Q4 then act as diodes. The diff amp formed by Q5-Q6 the load capacitance should be less than 500pF with a 5V operates normally, however, the input bias current in- supply and less than 100pF with a 30V supply. creases to the emitter current of Q5-Q6, which is typically
Rail-to-Rail Operation
180nA. The graph, Input Bias Current vs Common Mode Voltage found in the Typical Performance Characteristics The simplified schematic, Figure 3, details the circuit section, shows these transitions at three temperatures. design approach of the LT1672/LT1673/LT1674. The amplifier topology is a three-stage design consisting of a The collector currents of the two-input pairs are combined rail-to-rail input stage, that continues to operate with the in the second stage consisting of Q11 to Q16, which inputs above the positive rail, a folded cascode second furnishes most of the voltage gain. Capacitor C1 sets the stage that develops most of the voltage gain, and a rail-to- amplifier bandwidth. The output stage is configured for rail common emitter stage that provides the current gain. maximum swing by the use of common emitter output devices Q21 and Q22. Diodes D4 to D6 and current source The input stage is formed by two diff amps Q1-Q2 and Q3- Q15 set the output quiescent current. Q6. For signals with a common mode voltage between VEE D1 D2 D3 D7 Q10 Q13 Q14 Q15 Q20 + I1 C1 Q21 IN+ OUT IN – Q1 Q2 Q3 Q4 Q7 (V +) – 0.8V Q16 Q17 Q19 Q11 D4 Q5 Q6 Q12 D5 D6 Q18 Q22 R1 R2 I Q9 Q8 2 1672/3/4 F03
Figure 3. Simplified Schematic
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U U W U APPLICATIO S I FOR ATIO
The device will not be damaged if the inputs are taken lower and (VCC – 0.8V), Q1 and Q2 are active. When the input than 300mV below the negative supply as long as the cur- common mode exceeds (VCC – 0.8V), Q7 turns on, rent out of the pin is limited to less than 10mA. However, diverting the current from diff amp Q1-Q2 to current the output phase is not guaranteed and the supply current mirror Q8-Q9. The current from Q8 biases on the other will increase. diff amp consisting of PNP’s Q5-Q6 and NPN’s Q3-Q4. Though Q5-Q6 are driven from the emitters rather than
Output
the base, the basic diff amp action is the same. When the common mode voltage is between (V The graph, Capacitive Load Handling, shows amplifier sta- CC – 0.8V) and VCC, devices Q3 and Q4 act as followers, forming a buffer bility with the output biased at half supply. If the output is between the amplifier inputs and the emitters of the Q5- to be operated within about 100mV of the positive rail, the Q6. If the common mode voltage is taken above V allowable load capacitance is less. With this output volt- CC, Schottky diodes D1 and D2 reverse bias and devices Q3 age, the worst case occurs at AV = 5 and light loads, where and Q4 then act as diodes. The diff amp formed by Q5-Q6 the load capacitance should be less than 500pF with a 5V operates normally, however, the input bias current in- supply and less than 100pF with a 30V supply. creases to the emitter current of Q5-Q6, which is typically
Rail-to-Rail Operation
180nA. The graph, Input Bias Current vs Common Mode Voltage found in the Typical Performance Characteristics The simplified schematic, Figure 3, details the circuit section, shows these transitions at three temperatures. design approach of the LT1672/LT1673/LT1674. The amplifier topology is a three-stage design consisting of a The collector currents of the two-input pairs are combined rail-to-rail input stage, that continues to operate with the in the second stage consisting of Q11 to Q16, which inputs above the positive rail, a folded cascode second furnishes most of the voltage gain. Capacitor C1 sets the stage that develops most of the voltage gain, and a rail-to- amplifier bandwidth. The output stage is configured for rail common emitter stage that provides the current gain. maximum swing by the use of common emitter output devices Q21 and Q22. Diodes D4 to D6 and current source The input stage is formed by two diff amps Q1-Q2 and Q3- Q15 set the output quiescent current. Q6. For signals with a common mode voltage between VEE D1 D2 D3 D7 Q10 Q13 Q14 Q15 Q20 + I1 C1 Q21 IN+ OUT IN – Q1 Q2 Q3 Q4 Q7 (V +) – 0.8V Q16 Q17 Q19 Q11 D4 Q5 Q6 Q12 D5 D6 Q18 Q22 R1 R2 I Q9 Q8 2 1672/3/4 F03
Figure 3. Simplified Schematic
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