Datasheet LT5514 (Analog Devices) - 9
Hersteller | Analog Devices |
Beschreibung | Ultralow Distortion IF Amplifier/ADC Driver with Digitally Controlled Gain |
Seiten / Seite | 20 / 9 — TYPICAL PERFOR A CE CHARACTERISTICS (Standard Mode) TA = 25. C, VCC = 5V, … |
Dateiformat / Größe | PDF / 287 Kb |
Dokumentensprache | Englisch |
TYPICAL PERFOR A CE CHARACTERISTICS (Standard Mode) TA = 25. C, VCC = 5V, VCCO = 5V,
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LT5514
W U TYPICAL PERFOR A CE CHARACTERISTICS (Standard Mode) TA = 25
°
C, VCC = 5V, VCCO = 5V, ENA = ENB = 3V, control input levels VIL = 0.6V, VIH = 3V unless otherwise noted. Test circuit shown in Figure 10 unless otherwise noted. Note 1: Subtract 0.75ns calibration delay from output plots to estimate the LT5514 group delay. Note 2: When specified, COUT is connected differentially across the LT5514 OUT+, OUT– output pins. Pulse Response vs COUT at Max Pulse Response vs Output Level at Pulse Response vs Attenuation, Gain. Output Level is 2VP-P into Max Gain. Indicated Voltage Output Level is 4VP-P at Max Gain 50
Ω
External Load Levels are into 50
Ω
External Load into 50
Ω
External Load
0pF COUT = 0.82pF COUT 0pF MAX GAIN 1pF 4VP-P 1.5dB STEP 1.8pF 3VP-P 3dB STEP 3.3pF 2VP-P INPUT 6dB STEP 4.7pF 12dB STEP INPUT 6.8pf 22pF TO 10pF INPUTS GROUND 11pF EACH 18pF OUTPUT RMATCH = 255Ω 2ns/DIV 5514 G27 2ns/DIV 5514 G28 1ns/DIV 5514 G29
Pulse Response vs Attenuation, Pulse Response vs Attenuation, Output Level is 2VP-P at Max Gain Output Level is 2VP-P at Max Gain into 50
Ω
External Load into 50
Ω
External Load
RMATCH = 255Ω RMATCH = 255Ω, COUT = 1.8pF MAX GAIN MAX GAIN 1.5dB STEP 1.5dB STEP 3dB STEP 3dB STEP 6dB STEP INPUT INPUT 6dB STEP 12dB STEP 12dB STEP 1ns/DIV 5514 G30 1ns/DIV 5514 G31
Pulse Response vs Attenuation, Pulse Response vs Attenuation, LT5514 Levels are: VIN = 66mVP-P, LT5514 Levels are: VIN = 66mVP-P, VOUT = 2VP-P at Max Gain VOUT = 4VP-P at Max Gain
ROUT = 100Ω ROUT = 200Ω MAX GAIN MAX GAIN 1.5dB STEP 1.5dB STEP 3dB STEP 3dB STEP 6dB STEP 6dB STEP INPUT 12dB STEP INPUT 12dB STEP FIGURE 9 TEST CIRCUIT FIGURE 9 TEST CIRCUIT 1ns/DIV 5514 G32 1ns/DIV 5514 G33 5514f 9