Datasheet LT6555 (Analog Devices) - 8

LT6555
U U W U APPLICATIO S I FOR ATIO Power Supplies
The DGND pin should not be pulled above the EN pin since The LT6555 is optimized for ±5V supplies but can be doing so will turn on an ESD protection diode. If the EN pin operated on as little as ±2.25V or a single 4.5V supply and voltage is forced a diode drop below the DGND pin, current as much as ±6V or a single 12V supply. Internally, each should be limited to 10mA or less. supply is independent to improve channel isolation.
Do
The enable/disable times of the LT6555 are fast when
not leave any supply pins disconnected or the part may
driven with a logic input. Turn on (from 50% EN input to
not function correctly!
50% output) typically occurs in less than 50ns. Turn off is slower, but is typically below 500ns.
Enable/Shutdown
The LT6555 has a shutdown mode controlled by the EN
Channel Select
pin and referenced to the DGND pin. If the amplifier will The SEL pin uses the same internal threshold as the EN pin be enabled at all times, the EN pin can be connected and is also referenced to DGND. When the pin is logic low, directly to DGND. If the enable function is desired, either the channel A inputs are passed to the output. When the driving the pin above 2V or allowing the internal 46k pull- pin is logic high, the channel B inputs are passed to the up resistor to pull the EN pin to the top rail will disable the output. The pin should not be floated but can be tied to amplifier. When disabled, the DC output impedance will DGND to force the outputs to always be channel A or to V+ rise to approximately 360Ω through the internal feedback (when less than 8V) to force the outputs to always be and gain resistors. Supply current into the amplifier in the channel B. disabled state will be:
Truth Table
V+ V V+ – – V–
SEL A/B EN OUT
I EN S = + k 46 k 80 0 0 2 × IN A 1 0 2 × IN B It is important that the following constraints on the DGND, X 1 OFF EN and SEL pins are always followed:
V+ – VDGND
≥
4.5V Input Considerations VEN – VDGND
≤
5.5V V
The LT6555 uses input clamps referenced to the V
SEL – VDGND
≤
8V
REF pin to prevent damage to the input stage on the unselected In dual supply cases where V+ is less than 4.5V, DGND channel. Three transistors in series limit the input voltage should be connected to a potential below ground, such as to within three diode drops (±) from VREF. VREF is nomi- V–. Since the EN and SEL pins are referenced to DGND, nally set to half of the sum of the supplies by the 40k they may need to be pulled below ground in those cases. resistors. A simplified schematic is shown in Figure 1. In single supply applications above 5.5V, an additional To improve clamping, the pin’s DC impedance should be resistor may be needed from the EN pin to DGND if the pin minimized by connecting the VREF pin directly to ground in is ever allowed to float. For example, on a 12V single the symmetric dual supply case with a common mode supply, a 33k resistor would protect the pin from floating voltage of 0V. While loaded output swing limits the useful too high while still allowing the internal pull-up resistor to input voltage range in that case, if the common mode disable the part. voltage is not centered at ground or the input voltage On dual ±2.25V supplies, connecting the DGND pin to V– exceeds plus or minus three diodes from ground, an is the only way of ensuring that V+ – VDGND ≥ 4.5V. external resistor to either supply can be added to shift the 6555f 8