Datasheet LT6556 (Analog Devices) - 7

LT6556
U U U PI FU CTIO S (GN24 Package) IN1A (Pin 1):
Channel 1 Input A. This pin has a nominal be connected externally. Proper supply bypassing is impedance of 500kΩ and does not have any internal necessary for best performance. See the Applications termination resistor. Information section.
DGND (Pin 2):
Digital Ground Reference for Enable Pin.
V– (Pin 15):
Negative Supply Voltage for Channel 3 Output This pin is normally connected to ground. Stage. V– pins are not internally connected to each other and must all be connected externally. Proper supply bypassing
IN2A (Pin 3):
Channel 2 Input A. This pin has a nominal is necessary for best performance. See the Applications impedance of 500kΩ and does not have any internal Information section. termination resistor.
OUT3 (Pin 16):
Channel 3 Output. It is the buffered output
VREF (Pin 4):
Voltage Reference for Input Clamping. This of the selected Channel 3 input. is the tap to an internal voltage divider that defi nes mid- supply. It is normally connected to ground in dual supply,
V+ (Pin 17):
Positive Supply Voltage for Channels 2 and DC coupled applications. 3 Output Stages. V+ pins are not internally connected to each other and must all be connected externally. Proper
IN3A (Pin 5):
Channel 3 Input A. This pin has a nominal supply bypassing is necessary for best performance. See impedance of 500kΩ and does not have any internal the Applications Information section. termination resistor.
OUT2 (Pin 18):
Channel 2 Output. It is the buffered output
AGND (Pin 6):
Analog Ground for Isolation between IN3A of the selected Channel 2 input. and IN1B. AGND pins have ESD protection and should not be connected to potentials outside the power supply range.
V– (Pin 19):
Negative Supply Voltage for Channels 1 and 2 Output Stages. V– pins are not internally connected to
IN1B (Pin 7):
Channel 1 Input B. This pin has a nominal each other and must all be connected externally. Proper impedance of 500kΩ and does not have any internal supply bypassing is necessary for best performance. See termination resistor. the Applications Information section.
AGND (Pin 8):
Analog Ground for Isolation between IN1B
OUT1 (Pin 20):
Channel 1 Output. It is the buffered output and IN2B. AGND pins have ESD protection and should not be of the selected Channel 1 input. connected to potentials outside the power supply range.
V+ (Pin 21):
Positive Supply Voltage for Channel 1 Output
IN2B (Pin 9):
Channel 2 Input B. This pin has a nominal Stage. V+ pins are not internally connected to each other and impedance of 500kΩ and does not have any internal must all be connected externally. Proper supply bypassing termination resistor. is necessary for best performance. See the Applications
AGND (Pin 10):
Analog Ground for Isolation between Information section. IN2B and IN3B. AGND pins have ESD protection and
SEL
⎯
A/B (Pin 22):
Select Pin. This high impedance pin should not be connected to potentials outside the power selects which set of inputs are sent to the output pins. supply range. When the pin is pulled low, the A inputs are selected. When
IN3B (Pin 11):
Channel 3 Input B. This pin has a nominal the pin is pulled high, the B inputs are selected. impedance of 500kΩ and does not have any internal ⎯
E
⎯
N (Pin 23):
Enable Control Pin. An internal pull-up resistor termination resistor. of 46k defi nes the pin’s impedance and will turn the part
V– (Pin 12):
Negative Supply Voltage. V– pins are not in- off if the pin is unconnected. When the pin is pulled low, ternally connected to each other and must all be connected the amplifi ers are enabled. externally. Proper supply bypassing is necessary for best
Exposed Pad (Pin 25, QFN Only):
The Exposed Pad is performance. See the Applications Information section. V– and must be soldered to the PCB. It is internally con-
V+ (Pins 13, 14, 24):
Positive Supply Voltage. V+ pins nected to the QFN Pin 4, V–. are not internally connected to each other and must all 6556f 7