Datasheet LT1398, LT1399, LT1399HV (Analog Devices) - 10

LT1398/LT1399/LT1399HV
O U U W U APPLICATI S I FOR ATIO Power Supplies
will remain enabled at all times, then the EN pin should be tied to the V – supply. The enable pin current is approxi- The LT1398/LT1399 will operate from single or split mately 30µA when activated. If using CMOS open-drain supplies from ±2V (4V total) to ±6V (12V total). The logic, an external 1k pull-up resistor is recommended to LT1399HV will operate from single or split supplies from ± ensure that the LT1399 remains disabled in spite of any 2V (4V total) to ±7.5V (15V total). It is not necessary to CMOS drain-leakage currents. use equal value split supplies, however the offset voltage and inverting input bias current will change. The offset 5.0 T voltage changes about 600µV per volt of supply mis- A = 25°C 4.5 V + = 5V match. The inverting bias current will typically change 4.0 V – = 0V about 2µA per volt of supply mismatch. 3.5 3.0 V – = – 5V
Slew Rate
(mA) 2.5 S+I 2.0 Unlike a traditional voltage feedback op amp, the slew rate 1.5 of a current feedback amplifier is not independent of the 1.0 amplifier gain configuration. In a current feedback ampli- 0.5 fier, both the input stage and the output stage have slew rate 0 0 1 2 3 4 5 6 7 limitations. In the inverting mode, and for gains of 2 or more V + – VEN (V) in the noninverting mode, the signal amplitude between the 1398/99 F01 input pins is small and the overall slew rate is that of the
Figure 1. + IS vs (V+ – VEN)
output stage. For gains less than 2 in the noninverting mode, the overall slew rate is limited by the input stage. OUTPUT The input slew rate of the LT1398/LT1399/LT1399HV is approximately 600V/µs and is set by internal currents and capacitances. The output slew rate is set by the value of the feedback resistor and internal capacitance. At a gain of 2 with 324Ω feedback and gain resistors and ±5V supplies, the output slew rate is typically 800V/µs. Larger feedback resistors will reduce the slew rate as will lower supply EN voltages. VS = ±5V RF = 324Ω RL = 100Ω 1398/99 F02 VIN = 1V RG = 324Ω
Enable/ Disable Figure 2. Amplifier Enable Time, AV = 2
Each amplifier of the LT1398/LT1399/LT1399HV has a unique high impedance, zero supply current mode which is controlled by its own EN pin. These amplifiers are designed to operate with CMOS logic; the amplifiers draw OUTPUT zero current when these pins are high. To activate each amplifier, its EN pin is normally pulled to a logic low. However, supply current will vary as the voltage between the V + supply and EN is varied. As seen in Figure 1, +IS does vary with (V + – VEN), particularly when the voltage EN difference is less than 3V. For normal operation, it is VS = ±5V RF = 324Ω RL = 100Ω 1398/99 F03 important to keep the EN pin at least 3V below the V + VIN = 1V RG = 324Ω supply. If a V + of less than 3V is desired, and the amplifier
Figure 3. Amplifier Disable Time, AV = 2
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