Datasheet LTC6915 (Analog Devices) - 6
| Hersteller | Analog Devices |
| Beschreibung | Zero Drift, Precision Instrumentation Amplifier with Digitally Programmable Gain |
| Seiten / Seite | 18 / 6 — elecTrical characTerisTics. The. denotes the specifications which apply … |
| Dateiformat / Größe | PDF / 297 Kb |
| Dokumentensprache | Englisch |
elecTrical characTerisTics. The. denotes the specifications which apply over the full operating
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LTC6915
elecTrical characTerisTics The
l
denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. Timing, V+ = 4.5V to 5.5V, V– = 0V (Note 7)
t1 DIN Valid to CLK Setup l 30 ns t2 DIN Valid to CLK Hold l 0 ns t3 CLK Low l 50 ns t4 CLK High l 50 ns t5 CS/LD Pulse Width l 40 ns t6 LSB CLK to CS/LD l 40 ns t7 CS/LD Low to CLK l 20 ns t8 DOUT Output Delay CL = 15pF l 85 ns t9 CLK Low to CS/LD Low l 0 ns
Timing, Dual ±4.5V to ±5.5V Supplies (Note 7)
t1 DIN Valid to CLK Setup l 30 ns t2 DIN Valid to CLK Hold l 0 ns t3 CLK High l 50 ns t4 CLK Low l 50 ns t5 CS/LD Pulse Width l 40 ns t6 LSB CLK to CS/LD l 40 ns t7 CS/LD Low to CLK l 20 ns t8 DOUT Output Delay CL = 15pF l 85 ns t9 CLK Low to CS/LD Low l 0 ns
Note 1:
Stresses beyond those listed under Absolute Maximum Ratings
Note 4:
If the total source resistance is less than 10k, no DC errors result may cause permanent damage to the device. Exposure to any Absolute from the input bias current or mismatch of the input bias currents or the Maximum Rating condition for extended periods may affect device mismatch of the resistances connected to IN– and IN+. reliability and lifetime.
Note 5:
The PSRR measurement accuracy depends on the proximity of
Note 2:
These parameters are tested at ±5V supply; at 3V and 5V supplies the power supply bypass capacitor to the device under test. Because of they are guaranteed by design. this, the PSRR is 100% tested to relaxed limits at final test. However, their
Note 3:
These parameters are guaranteed by design. Thermocouple effects values are guaranteed by design to meet the data sheet limits. preclude measurement of these voltage levels in high speed automatic test
Note 6:
Supply current is dependent on the clock frequency. A higher clock systems. VOS is measured to a limit set by test equipment capability. frequency results in higher supply current.
Note 7:
Guaranteed by design, not subject to test. 6915fb 6 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Typical Performance Characteristics Pin Functions Block Diagrams Timing Diagram Operation Typical Application Package Description Revision History Typical Application Related Parts
elecTrical characTerisTics The
l
denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. Timing, V+ = 4.5V to 5.5V, V– = 0V (Note 7)
t1 DIN Valid to CLK Setup l 30 ns t2 DIN Valid to CLK Hold l 0 ns t3 CLK Low l 50 ns t4 CLK High l 50 ns t5 CS/LD Pulse Width l 40 ns t6 LSB CLK to CS/LD l 40 ns t7 CS/LD Low to CLK l 20 ns t8 DOUT Output Delay CL = 15pF l 85 ns t9 CLK Low to CS/LD Low l 0 ns
Timing, Dual ±4.5V to ±5.5V Supplies (Note 7)
t1 DIN Valid to CLK Setup l 30 ns t2 DIN Valid to CLK Hold l 0 ns t3 CLK High l 50 ns t4 CLK Low l 50 ns t5 CS/LD Pulse Width l 40 ns t6 LSB CLK to CS/LD l 40 ns t7 CS/LD Low to CLK l 20 ns t8 DOUT Output Delay CL = 15pF l 85 ns t9 CLK Low to CS/LD Low l 0 ns
Note 1:
Stresses beyond those listed under Absolute Maximum Ratings
Note 4:
If the total source resistance is less than 10k, no DC errors result may cause permanent damage to the device. Exposure to any Absolute from the input bias current or mismatch of the input bias currents or the Maximum Rating condition for extended periods may affect device mismatch of the resistances connected to IN– and IN+. reliability and lifetime.
Note 5:
The PSRR measurement accuracy depends on the proximity of
Note 2:
These parameters are tested at ±5V supply; at 3V and 5V supplies the power supply bypass capacitor to the device under test. Because of they are guaranteed by design. this, the PSRR is 100% tested to relaxed limits at final test. However, their
Note 3:
These parameters are guaranteed by design. Thermocouple effects values are guaranteed by design to meet the data sheet limits. preclude measurement of these voltage levels in high speed automatic test
Note 6:
Supply current is dependent on the clock frequency. A higher clock systems. VOS is measured to a limit set by test equipment capability. frequency results in higher supply current.
Note 7:
Guaranteed by design, not subject to test. 6915fb 6 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Typical Performance Characteristics Pin Functions Block Diagrams Timing Diagram Operation Typical Application Package Description Revision History Typical Application Related Parts