Datasheet AD8369 (Analog Devices) - 2

AD8369–SPECIFICATIONS (VS = 5 V, T = 25
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C, RS = 200
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, RL = 1000
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, Frequency = 70 MHz, at maximum gain, unless otherwise noted.) Parameter Conditions Min Typ Max Unit
OVERALL FUNCTION Frequency Range 3 dB Bandwidth LF* 600 MHz GAIN CONTROL INTERFACE Voltage Gain Span 45 dB Maximum Gain All bits high (1 1 1 1) 40 dB Minimum Gain All bits low (0 0 0 0) –5 dB Gain Step Size 3 dB Gain Step Accuracy Over entire gain range, with respect to 3 dB step ±0.05 dB Gain Step Response Time Step = 3 dB, settling to 10% of final value 30 ns INPUT STAGE Input Resistance From INHI to INLO 200 W From INHI to COMM, from INLO to COMM 100 W Input Capacitance From INHI to INLO 0.1 pF From INHI to COMM, from INLO to COMM 1.1 pF Input Noise Spectral Density 2 nV/÷Hz Input Common-Mode DC Voltage Measured at pin CMDC 1.7 V Maximum Linear Input |VINHI – VINLO| at Minimum Gain 2.2 V OUTPUT STAGE Output Resistance From OPHI to OPLO 200 W From OPHI to COMM, from OPLO to COMM 100 W Output Capacitance From OPHI to OPLO 0.25 pF From OPHI to COMM, from OPLO to COMM 1.5 pF Common-Mode DC Voltage No input signal VS/2 V Slew Rate Output step = 1 V 1200 V/ms POWER INTERFACE Supply Voltage 3.0 5.5 V Quiescent Current PWUP high 37 42 mA vs. Temperature –40rC £ TA £ 85rC 52 mA Disable Current PWUP low 400 750 mA vs. Temperature –40rC £ TA £ 85rC 1 mA POWER UP INTERFACE Pin PWUP Enable Threshold 1.0 V Disable Threshold 2.2 V Response Time Time delay following low to high transition 7 ms on PWUP until output settles to within 10% of final value Input Bias Current PWUP = 5 V 160 mA DIGITAL INTERFACE Pins SENB, BIT0, BIT1, BIT2, BIT3, and DENB Low Condition 2.0 V High Condition 3.0 V Input Bias Current Low input 150 mA Frequency = 10 MHz Voltage Gain 40.5 dB Gain Flatness Within ± 10 MHz of 10 MHz +0.05* dB Noise Figure 7.0 dB Output IP3 f1 = 9.945 MHz, f2 = 10.550 MHz +22 dBV rms +22 dBm IMD3 f1 = 9.945 MHz, f2 = 10.550 MHz VOPHI – VOPLO = 1 V p-p composite –74 dBc Harmonic Distortion Second-Order, VOPHI – VOPLO = 1 V p-p –72 dBc Third-Order, VOPHI – VOPLO = 1 V p-p –71 dBc P1dB For ± 1 dB deviation from linear gain +3 dBV rms +3 dBm *The low frequency high-pass corner is determined by the capacitor on pin FILT, C FILT. See the Theory of Operation section for details. –2– REV. A Document Outline Features Applications Functional Block Diagram Product Description Specifications Timing Specifications Absolute Maximum Ratings Pin Configuration Typical Performance Characteristics Theroy of Operation Input Attentuator and Output 3 dB Step Fixed Gain Amplifier Input and Output Interfaces Noise and Distortion Offset Control Loop Digital Control Basic Connections Input-Output Interface Reducing Gain Sensitivity to Input and Output Impedance Variation Operation from a Single-Sided Source Interfacing to an ADC PCB Layout Considerations Evaluation Board Evaluation Board Software Appendix Characterization Equipment Definitions of Selected Parameters Composite Waveform Assumption Outline Dimensions Ordering Guide Revision History