Datasheet LT6600-2.5 (Analog Devices) - 7
| Hersteller | Analog Devices |
| Beschreibung | Very Low Noise, Differential Amplifi er and 2.5MHz Lowpass Filter |
| Seiten / Seite | 16 / 7 — PIN FUNCTIONS (DFN/SO). IN– and IN+ (Pins 1, 12/Pins 1, 8):. OUT+ and … |
| Dateiformat / Größe | PDF / 233 Kb |
| Dokumentensprache | Englisch |
PIN FUNCTIONS (DFN/SO). IN– and IN+ (Pins 1, 12/Pins 1, 8):. OUT+ and OUT– (Pins 6, 7/Pins 4, 5):. NC (Pins 2, 5, 11/NA):
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Textversion des Dokuments
LT6600-2.5
PIN FUNCTIONS (DFN/SO) IN– and IN+ (Pins 1, 12/Pins 1, 8):
Input Pins. Signals can should be as close as possible to the IC. For dual supply be applied to either or both input pins through identical applications, bypass V+ to ground and V– to ground with external resistors, RIN. The DC gain from differential inputs a quality 0.1μF ceramic capacitor. to the differential outputs is 1580Ω/RIN.
OUT+ and OUT– (Pins 6, 7/Pins 4, 5):
Output Pins. These
NC (Pins 2, 5, 11/NA):
No Connection are the fi lter differential outputs. Each pin can drive a 100Ω and/or 50pF load to AC ground.
VOCM (Pin 3/Pin 2):
DC Common Mode Reference Voltage- for the 2nd Filter Stage. Its value programs the common
VMID (Pin 10/Pin 7):
The VMID pin is internally biased at mode voltage of the differential output of the fi lter. This mid-supply, see Block Diagram. For single supply op- is a high impedance input, which can be driven from an eration, the VMID pin should be bypassed with a quality external voltage reference, or it can be tied to VMID on the 0.01μF ceramic capacitor to V–. For dual supply operation, PC board. VOCM should be bypassed with a 0.01μF ceramic VMID can be bypassed or connected to a high quality DC capacitor unless it is connected to a ground plane. ground. A ground plane should be used. A poor ground will increase noise and distortion. V
V+ and V– (Pins 4, 8, 9/Pins 3, 6):
Power Supply Pins. For MID sets the output common mode voltage of the 1st stage of the fi lter. It has a single 3.3V or 5V supply (V– grounded) a quality 0.1μF a 5.5kΩ impedance, and it can be overridden with an ceramic bypass capacitor is required from the positive external low impedance voltage source. supply pin (V+) to the negative supply pin (V–). The bypass
BLOCK DIAGRAM
RIN V + IN IN+ OUT– V– VMID V+ 11k PROPRIETARY LOWPASS 1580Ω FILTER STAGE 11k 800Ω V– OP AMP 800Ω + – + – V V OCM OCM – + – + 800Ω 800Ω 1580Ω 660025 BD V – IN V IN– OCM V+ OUT+ RIN 660025fe 7
PIN FUNCTIONS (DFN/SO) IN– and IN+ (Pins 1, 12/Pins 1, 8):
Input Pins. Signals can should be as close as possible to the IC. For dual supply be applied to either or both input pins through identical applications, bypass V+ to ground and V– to ground with external resistors, RIN. The DC gain from differential inputs a quality 0.1μF ceramic capacitor. to the differential outputs is 1580Ω/RIN.
OUT+ and OUT– (Pins 6, 7/Pins 4, 5):
Output Pins. These
NC (Pins 2, 5, 11/NA):
No Connection are the fi lter differential outputs. Each pin can drive a 100Ω and/or 50pF load to AC ground.
VOCM (Pin 3/Pin 2):
DC Common Mode Reference Voltage- for the 2nd Filter Stage. Its value programs the common
VMID (Pin 10/Pin 7):
The VMID pin is internally biased at mode voltage of the differential output of the fi lter. This mid-supply, see Block Diagram. For single supply op- is a high impedance input, which can be driven from an eration, the VMID pin should be bypassed with a quality external voltage reference, or it can be tied to VMID on the 0.01μF ceramic capacitor to V–. For dual supply operation, PC board. VOCM should be bypassed with a 0.01μF ceramic VMID can be bypassed or connected to a high quality DC capacitor unless it is connected to a ground plane. ground. A ground plane should be used. A poor ground will increase noise and distortion. V
V+ and V– (Pins 4, 8, 9/Pins 3, 6):
Power Supply Pins. For MID sets the output common mode voltage of the 1st stage of the fi lter. It has a single 3.3V or 5V supply (V– grounded) a quality 0.1μF a 5.5kΩ impedance, and it can be overridden with an ceramic bypass capacitor is required from the positive external low impedance voltage source. supply pin (V+) to the negative supply pin (V–). The bypass
BLOCK DIAGRAM
RIN V + IN IN+ OUT– V– VMID V+ 11k PROPRIETARY LOWPASS 1580Ω FILTER STAGE 11k 800Ω V– OP AMP 800Ω + – + – V V OCM OCM – + – + 800Ω 800Ω 1580Ω 660025 BD V – IN V IN– OCM V+ OUT+ RIN 660025fe 7