Datasheet AD8370 (Analog Devices) - 6
| Hersteller | Analog Devices |
| Beschreibung | 750 MHz Digitally Controlled Variable Gain Amplifier |
| Seiten / Seite | 28 / 6 — AD8370. Data Sheet. PIN CONFIGURATION AND FUNCTION DESCRIPTIONS. INHI. 16 … |
| Revision | B |
| Dateiformat / Größe | PDF / 786 Kb |
| Dokumentensprache | Englisch |
AD8370. Data Sheet. PIN CONFIGURATION AND FUNCTION DESCRIPTIONS. INHI. 16 INLO. ICOM. 15 ICOM. VCCI. DATA. PWUP. TOP VIEW. 13 CLCK
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Textversion des Dokuments
AD8370 Data Sheet PIN CONFIGURATION AND FUNCTION DESCRIPTIONS INHI 1 16 INLO ICOM 2 15 ICOM VCCI 3 14 AD8370 DATA PWUP 4 TOP VIEW 13 CLCK (Not to Scale) VOCM 5 12 LTCH VCCO 6 11 VCCO OCOM 7 10 OCOM OPHI 8 9 OPLO
03692-003 Figure 3.16-Lead TSSOP
Table 3. Pin Function Descriptions Pin No. Mnemonic Description
1 INHI Balanced Differential Input. Internally biased. 2, 15, PADDLE ICOM Input Common. Connect to a low impedance ground. This node is also connected to the exposed pad on the bottom of the device. 3 VCCI Input Positive Supply. 3.0 V to 5.5 V. Should be properly bypassed. 4 PWUP Power Enable Pin. Device is operational when PWUP is pulled high. 5 VOCM Common-Mode Output Voltage Pin. The midsupply ((VVCCO − VOCOM)/2) common-mode voltage is delivered to this pin for external bypassing for additional common-mode supply decoupling. This can be achieved with a bypass capacitor to ground. This pin is an output only and is not to be driven externally. 6, 11 VCCO Output Positive Supply. 3.0 V to 5.5 V. Should be properly bypassed. 7, 10 OCOM Output Common. Connect to a low impedance ground. 8 OPHI Balanced Differential Output. Biased to midsupply. 9 OPLO Balanced Differential Output. Biased to midsupply. 12 LTCH Serial Data Latch Pin. Serial data is clocked into the shift register via the DATA pin when LTCH is low. Data in shift register is latched on the next high-going edge. 13 CLCK Serial Clock Input Pin. 14 DATA Serial Data Input Pin. 16 INLO Balanced Differential Input. Internally biased. Rev. B | Page 6 of 28 Document Outline Features Applications General Description Functional Block Diagram Table of Contents Revision History Specifications Absolute Maximum Ratings ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Theory of Operation Block Architecture Preamplifier Transconductance Stage Output Amplifier Digital Interface and Timing Applications Basic Connections Gain Codes Power-Up Feature Choosing Between Gain Ranges Layout and Operating Considerations Package Considerations Single-Ended-to-Differential Conversion DC-Coupled Operation ADC Interfacing 3 V Operation Evaluation Board and Software Appendix Characterization Equipment Composite Waveform Assumption Definitions of Selected Parameters Outline Dimensions Ordering Guide
03692-003 Figure 3.16-Lead TSSOP
Table 3. Pin Function Descriptions Pin No. Mnemonic Description
1 INHI Balanced Differential Input. Internally biased. 2, 15, PADDLE ICOM Input Common. Connect to a low impedance ground. This node is also connected to the exposed pad on the bottom of the device. 3 VCCI Input Positive Supply. 3.0 V to 5.5 V. Should be properly bypassed. 4 PWUP Power Enable Pin. Device is operational when PWUP is pulled high. 5 VOCM Common-Mode Output Voltage Pin. The midsupply ((VVCCO − VOCOM)/2) common-mode voltage is delivered to this pin for external bypassing for additional common-mode supply decoupling. This can be achieved with a bypass capacitor to ground. This pin is an output only and is not to be driven externally. 6, 11 VCCO Output Positive Supply. 3.0 V to 5.5 V. Should be properly bypassed. 7, 10 OCOM Output Common. Connect to a low impedance ground. 8 OPHI Balanced Differential Output. Biased to midsupply. 9 OPLO Balanced Differential Output. Biased to midsupply. 12 LTCH Serial Data Latch Pin. Serial data is clocked into the shift register via the DATA pin when LTCH is low. Data in shift register is latched on the next high-going edge. 13 CLCK Serial Clock Input Pin. 14 DATA Serial Data Input Pin. 16 INLO Balanced Differential Input. Internally biased. Rev. B | Page 6 of 28 Document Outline Features Applications General Description Functional Block Diagram Table of Contents Revision History Specifications Absolute Maximum Ratings ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Theory of Operation Block Architecture Preamplifier Transconductance Stage Output Amplifier Digital Interface and Timing Applications Basic Connections Gain Codes Power-Up Feature Choosing Between Gain Ranges Layout and Operating Considerations Package Considerations Single-Ended-to-Differential Conversion DC-Coupled Operation ADC Interfacing 3 V Operation Evaluation Board and Software Appendix Characterization Equipment Composite Waveform Assumption Definitions of Selected Parameters Outline Dimensions Ordering Guide