41 dB Range, 1 dB Step Size, Programmable Dual VGA
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16 /9 — Data Sheet. AD8372. V = 0dB. B) d (. AV = 10dB. E UR. IG F. AV = 20dB. IS …
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C
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Englisch
Data Sheet. AD8372. V = 0dB. B) d (. AV = 10dB. E UR. IG F. AV = 20dB. IS NO. AV = 32dB. 100. 120. 140. 160. 180. 200. 20ns/DIV. FREQUENCY (MHz). –10. –20. –30
Data SheetAD83725045A40V = 0dB35B) d (30AV = 10dBE UR25IG FAV = 20dBE20IS NO1510AV = 32dB 1 5 01 1- 05 0 07 20406080100120140160180200 2 020ns/DIV -01 051 FREQUENCY (MHz) 07 Figure 11. Noise Figure vs. Frequency Figure 13. AD8372 Response to 6 dB Step Change in Gain (Gain Register Setting 36 to Setting 42); Falling Edge Shown is Serial Clock Input Edge 0–10–20–30–40) B (d –50–60–70–80–90 3 1M10M100M1G 01 1- 05 FREQUENCY (Hz) 07 Figure 12. Isolation, Input to Opposite Output at Maximum Gain (To calculate output to output gain, subtract 29 dB from this plot) Rev. C | Page 9 of 16 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION REVISION HISTORY SPECIFICATIONS SERIAL CONTROL INTERFACE TIMING ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION SINGLE-ENDED AND DIFFERENTIAL SIGNALS PASSIVE FILTER TECHNIQUES DIGITAL GAIN CONTROL DRIVING ANALOG-TO-DIGITAL CONVERTERS EVALUATION BOARD SCHEMATIC OUTLINE DIMENSIONS ORDERING GUIDE