Datasheet LT1777 (Analog Devices) - 6
| Hersteller | Analog Devices |
| Beschreibung | Low Noise Step-Down Switching Regulator |
| Seiten / Seite | 24 / 6 — PIN FUNCTIONS. GND (Pins 1, 8, 9, 16):. VSW (Pin 6):. NC (Pins 2, 11, … |
| Dateiformat / Größe | PDF / 286 Kb |
| Dokumentensprache | Englisch |
PIN FUNCTIONS. GND (Pins 1, 8, 9, 16):. VSW (Pin 6):. NC (Pins 2, 11, 15):. SGND (Pin 7):. SHDN (Pin 3):. VIN (Pin 10):
Modelllinie für dieses Datenblatt
Textversion des Dokuments
LT1777
U U U PIN FUNCTIONS GND (Pins 1, 8, 9, 16):
These corner package pins are removed or supplied accordingly to limit dI/dt (see Appli- mechanically connected to the die paddle and thus aid in cations Information). conducting away internally generated heat. As these are
VSW (Pin 6):
This is the emitter node of the output switch electrically connected to the die substrate, they must be and has large currents flowing through it. Keep the traces held at ground potential. A direct connection to the local to the switching components as short as possible to ground plane is recommended. minimize electromagnetic radiation and voltage spikes.
NC (Pins 2, 11, 15):
Package Pins 2, 11 and 15 are
SGND (Pin 7):
This is the device signal ground pin. The unconnected. internal reference and feedback amplifier are referred to it.
SHDN (Pin 3):
When pulled below the shutdown mode Keep the ground path connection to the FB divider and the threshold, nominally 0.5V, this pin turns off the regulator VC compensation capacitor free of large ground currents. and reduces VIN input current to a few tens of microam-
VIN (Pin 10):
This is the high voltage supply pin for the peres (shutdown mode). output switch. It also supplies power to the internal control When this pin is held above the shutdown mode threshold, circuitry during start-up conditions or if the VCC pin is left but below the lockout threshold, the part will be opera- open. A high quality bypass capacitor which meets the tional with the exception that output switching action will input ripple current requirements is needed here (see be inhibited (lockout mode). A user-adjustable undervolt- Applications Information). age lockout can be implemented by driving this pin from
SYNC (Pin 12):
Pin to synchronize internal oscillator to an external resistor divider to VIN. This action is logically external frequency reference. It is directly logic compat- “ANDed” with the internal UVLO, nominally set at 6.7V, ible and can be driven with any signal between 10% and such that minimum VIN can be increased above 6.7V, but 90% duty cycle. The sync function is internally disabled if not decreased (see Applications Information). the FB pin voltage is low enough to cause oscillator If unused, this pin should be left open. However, the high slowdown. If unused, this pin should be grounded. impedance nature of this pin renders it susceptible to
FB (Pin 13):
This is the inverting input to the feedback coupling from the VSW node, so a small capacitor to amplifier. The noninverting input of this amplifier is inter- ground, typically 100pF or so is recommended when the nally tied to the 1.24V reference. This pin also slows down pin is left open. the frequency of the internal oscillator when its voltage is
V
abnormally low, e.g. 2/3 of normal or less. This feature
CC: (Pin 4):
Pin to power the internal control circuitry from the switching supply output. Proper use of this pin helps maintain proper short-circuit protection. Coupling enhances overall power supply efficiency. During start-up from high speed noise to this pin can cause irregular conditions, internal control circuitry is powered directly operation. (See Switch Node Considerations section.) from VIN. If the output capacitor is located more than an
VC (Pin 14):
This is the control voltage pin which is the inch from the VCC pin, a separate 0.1µF bypass capacitor output of the feedback amplifier and the input of the to ground may be required right at the pin. current comparator. Frequency compensation of the over-
V
all loop is effected by placing a capacitor (or in most cases
D (Pin 5):
This pin is used in conjunction with a small external sense inductor to limit power path dI/dt. The a series R/C combination) between this node and ground. sense inductor is placed between the V Coupling from high speed noise to this pin can cause SW output node and the cathode of the freewheeling (power) diode, and the V irregular operation. (See Switch Node Considerations D pin is connected to the diode. As the voltage across the section.) inductor reaches ±2VBE, drive to the output transistor is 6
U U U PIN FUNCTIONS GND (Pins 1, 8, 9, 16):
These corner package pins are removed or supplied accordingly to limit dI/dt (see Appli- mechanically connected to the die paddle and thus aid in cations Information). conducting away internally generated heat. As these are
VSW (Pin 6):
This is the emitter node of the output switch electrically connected to the die substrate, they must be and has large currents flowing through it. Keep the traces held at ground potential. A direct connection to the local to the switching components as short as possible to ground plane is recommended. minimize electromagnetic radiation and voltage spikes.
NC (Pins 2, 11, 15):
Package Pins 2, 11 and 15 are
SGND (Pin 7):
This is the device signal ground pin. The unconnected. internal reference and feedback amplifier are referred to it.
SHDN (Pin 3):
When pulled below the shutdown mode Keep the ground path connection to the FB divider and the threshold, nominally 0.5V, this pin turns off the regulator VC compensation capacitor free of large ground currents. and reduces VIN input current to a few tens of microam-
VIN (Pin 10):
This is the high voltage supply pin for the peres (shutdown mode). output switch. It also supplies power to the internal control When this pin is held above the shutdown mode threshold, circuitry during start-up conditions or if the VCC pin is left but below the lockout threshold, the part will be opera- open. A high quality bypass capacitor which meets the tional with the exception that output switching action will input ripple current requirements is needed here (see be inhibited (lockout mode). A user-adjustable undervolt- Applications Information). age lockout can be implemented by driving this pin from
SYNC (Pin 12):
Pin to synchronize internal oscillator to an external resistor divider to VIN. This action is logically external frequency reference. It is directly logic compat- “ANDed” with the internal UVLO, nominally set at 6.7V, ible and can be driven with any signal between 10% and such that minimum VIN can be increased above 6.7V, but 90% duty cycle. The sync function is internally disabled if not decreased (see Applications Information). the FB pin voltage is low enough to cause oscillator If unused, this pin should be left open. However, the high slowdown. If unused, this pin should be grounded. impedance nature of this pin renders it susceptible to
FB (Pin 13):
This is the inverting input to the feedback coupling from the VSW node, so a small capacitor to amplifier. The noninverting input of this amplifier is inter- ground, typically 100pF or so is recommended when the nally tied to the 1.24V reference. This pin also slows down pin is left open. the frequency of the internal oscillator when its voltage is
V
abnormally low, e.g. 2/3 of normal or less. This feature
CC: (Pin 4):
Pin to power the internal control circuitry from the switching supply output. Proper use of this pin helps maintain proper short-circuit protection. Coupling enhances overall power supply efficiency. During start-up from high speed noise to this pin can cause irregular conditions, internal control circuitry is powered directly operation. (See Switch Node Considerations section.) from VIN. If the output capacitor is located more than an
VC (Pin 14):
This is the control voltage pin which is the inch from the VCC pin, a separate 0.1µF bypass capacitor output of the feedback amplifier and the input of the to ground may be required right at the pin. current comparator. Frequency compensation of the over-
V
all loop is effected by placing a capacitor (or in most cases
D (Pin 5):
This pin is used in conjunction with a small external sense inductor to limit power path dI/dt. The a series R/C combination) between this node and ground. sense inductor is placed between the V Coupling from high speed noise to this pin can cause SW output node and the cathode of the freewheeling (power) diode, and the V irregular operation. (See Switch Node Considerations D pin is connected to the diode. As the voltage across the section.) inductor reaches ±2VBE, drive to the output transistor is 6