Datasheet LT1956, LT1956-5 (Analog Devices) - 6
| Hersteller | Analog Devices |
| Beschreibung | High Voltage, 1.5A, 500kHz Step-Down Switching Regulators |
| Seiten / Seite | 28 / 6 — PI FU CTIO S. GND (Pins 1, 8, 9, 16):. VC (Pin 11). FB/SENSE (Pin 12):. … |
| Dateiformat / Größe | PDF / 316 Kb |
| Dokumentensprache | Englisch |
PI FU CTIO S. GND (Pins 1, 8, 9, 16):. VC (Pin 11). FB/SENSE (Pin 12):. SW (Pin 2):. NC (Pins 3, 5, 7, 13):. SYNC (Pin 14):
Modelllinie für dieses Datenblatt
Textversion des Dokuments
LT1956/LT1956-5
U U U PI FU CTIO S GND (Pins 1, 8, 9, 16):
The GND pin connections act as
VC (Pin 11)
The VC pin is the output of the error amplifier the reference for the regulated output, so load regulation and the input of the peak switch current comparator. It is will suffer if the “ground” end of the load is not at the same normally used for frequency compensation, but can also voltage as the GND pins of the IC. This condition will occur serve as a current clamp or control loop override. VC sits when load current or other currents flow through metal at about 1V for light loads and 2V at maximum load. It can paths between the GND pins and the load ground. Keep the be driven to ground to shut off the regulator, but if driven paths between the GND pins and the load ground short high, current must be limited to 4mA. and use a ground plane when possible. For the FE package,
FB/SENSE (Pin 12):
The feedback pin is used to set the the exposed pad should be soldered to the copper GND output voltage using an external voltage divider that gen- plane underneath the device. (See Applications Informa- erates 1.22V at the pin for the desired output voltage. The tion—Layout Considerations.) 5V fixed output voltage parts have the divider included on
SW (Pin 2):
The switch pin is the emitter of the on-chip the chip and the FB pin is used as a SENSE pin, connected power NPN switch. This pin is driven up to the input pin directly to the 5V output. Three additional functions are voltage during switch on time. Inductor current drives the performed by the FB pin. When the pin voltage drops switch pin negative during switch off time. Negative volt- below 0.6V, switch current limit is reduced and the exter- age is clamped with the external catch diode. Maximum nal SYNC function is disabled. Below 0.8V, switching negative switch voltage allowed is – 0.8V. frequency is also reduced. See Feedback Pin Functions in Applications Information for details.
NC (Pins 3, 5, 7, 13):
No Connection.
SYNC (Pin 14):
The SYNC pin is used to synchronize the
VIN (Pin 4):
This is the collector of the on-chip power NPN internal oscillator to an external signal. It is directly logic switch. VIN powers the internal control circuitry when a compatible and can be driven with any signal between voltage on the BIAS pin is not present. High dI/dt edges 10% and 90% duty cycle. The synchronizing range is occur on this pin during switch turn on and off. Keep the equal to initial operating frequency up to 700kHz. See path short from the VIN pin through the input bypass Synchronizing in Applications Information for details. If capacitor, through the catch diode back to SW. All trace unused, this pin should be tied to ground. inductance on this path will create a voltage spike at switch off, adding to the V
SHDN (Pin 15):
The SHDN pin is used to turn off the CE voltage across the internal NPN. regulator and to reduce input current to a few microam-
BOOST (Pin 6):
The BOOST pin is used to provide a drive peres. This pin has two thresholds: one at 2.38V to disable voltage, higher than the input voltage, to the internal switching and a second at 0.4V to force complete mi- bipolar NPN power switch. Without this added voltage, the cropower shutdown. The 2.38V threshold functions as an typical switch voltage loss would be about 1.5V. The accurate undervoltage lockout (UVLO); sometimes used additional BOOST voltage allows the switch to saturate to prevent the regulator from delivering power until the and voltage loss approximates that of a 0.2Ω FET struc- input voltage has reached a predetermined level. ture, but with much smaller die area. If the SHDN pin functions are not required, the pin can
BIAS (Pin 10):
The BIAS pin is used to improve efficiency either be left open (to allow an internal bias current to lift when operating at higher input voltages and light load the pin to a default high state) or be forced high to a level current. Connecting this pin to the regulated output volt- not to exceed 6V. age forces most of the internal circuitry to draw its oper- ating current from the output voltage rather than the input supply. This architecture increases efficiency especially when the input voltage is much higher than the output. Minimum output voltage setting for this mode of operation is 3V. 1956f 6
U U U PI FU CTIO S GND (Pins 1, 8, 9, 16):
The GND pin connections act as
VC (Pin 11)
The VC pin is the output of the error amplifier the reference for the regulated output, so load regulation and the input of the peak switch current comparator. It is will suffer if the “ground” end of the load is not at the same normally used for frequency compensation, but can also voltage as the GND pins of the IC. This condition will occur serve as a current clamp or control loop override. VC sits when load current or other currents flow through metal at about 1V for light loads and 2V at maximum load. It can paths between the GND pins and the load ground. Keep the be driven to ground to shut off the regulator, but if driven paths between the GND pins and the load ground short high, current must be limited to 4mA. and use a ground plane when possible. For the FE package,
FB/SENSE (Pin 12):
The feedback pin is used to set the the exposed pad should be soldered to the copper GND output voltage using an external voltage divider that gen- plane underneath the device. (See Applications Informa- erates 1.22V at the pin for the desired output voltage. The tion—Layout Considerations.) 5V fixed output voltage parts have the divider included on
SW (Pin 2):
The switch pin is the emitter of the on-chip the chip and the FB pin is used as a SENSE pin, connected power NPN switch. This pin is driven up to the input pin directly to the 5V output. Three additional functions are voltage during switch on time. Inductor current drives the performed by the FB pin. When the pin voltage drops switch pin negative during switch off time. Negative volt- below 0.6V, switch current limit is reduced and the exter- age is clamped with the external catch diode. Maximum nal SYNC function is disabled. Below 0.8V, switching negative switch voltage allowed is – 0.8V. frequency is also reduced. See Feedback Pin Functions in Applications Information for details.
NC (Pins 3, 5, 7, 13):
No Connection.
SYNC (Pin 14):
The SYNC pin is used to synchronize the
VIN (Pin 4):
This is the collector of the on-chip power NPN internal oscillator to an external signal. It is directly logic switch. VIN powers the internal control circuitry when a compatible and can be driven with any signal between voltage on the BIAS pin is not present. High dI/dt edges 10% and 90% duty cycle. The synchronizing range is occur on this pin during switch turn on and off. Keep the equal to initial operating frequency up to 700kHz. See path short from the VIN pin through the input bypass Synchronizing in Applications Information for details. If capacitor, through the catch diode back to SW. All trace unused, this pin should be tied to ground. inductance on this path will create a voltage spike at switch off, adding to the V
SHDN (Pin 15):
The SHDN pin is used to turn off the CE voltage across the internal NPN. regulator and to reduce input current to a few microam-
BOOST (Pin 6):
The BOOST pin is used to provide a drive peres. This pin has two thresholds: one at 2.38V to disable voltage, higher than the input voltage, to the internal switching and a second at 0.4V to force complete mi- bipolar NPN power switch. Without this added voltage, the cropower shutdown. The 2.38V threshold functions as an typical switch voltage loss would be about 1.5V. The accurate undervoltage lockout (UVLO); sometimes used additional BOOST voltage allows the switch to saturate to prevent the regulator from delivering power until the and voltage loss approximates that of a 0.2Ω FET struc- input voltage has reached a predetermined level. ture, but with much smaller die area. If the SHDN pin functions are not required, the pin can
BIAS (Pin 10):
The BIAS pin is used to improve efficiency either be left open (to allow an internal bias current to lift when operating at higher input voltages and light load the pin to a default high state) or be forced high to a level current. Connecting this pin to the regulated output volt- not to exceed 6V. age forces most of the internal circuitry to draw its oper- ating current from the output voltage rather than the input supply. This architecture increases efficiency especially when the input voltage is much higher than the output. Minimum output voltage setting for this mode of operation is 3V. 1956f 6