Datasheet LT1976, LT1976B (Analog Devices) - 9

LT1976/LT1976B
U U U PI FU CTIO S CSS (Pin 9):
A capacitor from the CSS pin to the regulated
PGFB (PIN 13):
The PGFB pin is the positive input to a output voltage determines the output voltage ramp rate comparator whose negative input is set at VPGFB. When during start-up. When the current through the CSS capaci- PGFB is taken above VPGFB, current (ICSS) is sourced into tor exceeds the CSS threshold (ICSS), the voltage ramp of the CT pin starting the PG delay period. When the voltage the output is limited. The CSS threshold is proportional to on the PGFB pin drops below VPGFB, the CT pin is rapidly the FB voltage (see Typical Performance Characteristics) discharged resetting the PG delay period. The PGFB volt- and is defeated for FB voltage greater than 0.9V (typical). age is typically generated by a resistive divider from the See Soft-Start section in Applications Information for regulated output or input supply. See Power Good section details. in Applications Information for details.
BIAS (Pin 10):
The BIAS pin is used to improve efficiency
SYNC (Pin 14):
The SYNC pin is used to synchronize the when operating at higher input voltages and light load internal oscillator to an external signal. It is directly logic current. Connecting this pin to the regulated output volt- compatible and can be driven with any signal between age forces most of the internal circuitry to draw its 20% and 80% duty cycle. The synchronizing range is operating current from the output voltage rather than the equal to maximum initial operating frequency up to 700kHz. input supply. This architecture increases efficiency espe- When the voltage on the FB pin is below 0.9V the SYNC cially when the input voltage is much higher than the function is disabled. See the Synchronizing section in output. Minimum output voltage setting for this mode of Applications Information for details. operation is 3V.
SHDN (Pin 15):
The SHDN pin is used to turn off the
VC (Pin 11):
The VC pin is the output of the error amplifier regulator and to reduce input current to less than 1μA. The and the input of the peak switch current comparator. It is SHDN pin requires a voltage above 1.3V with a typical normally used for frequency compensation, but can also source current of 5μA to take the IC out of the shutdown serve as a current clamp or control loop override. The VC state. pin sits about 0.45V for light loads and 2.2V at current
PG (Pin 16):
The PG pin is functional only when the SHDN limit. The LT1976 clamps the VC pin slightly below the pin is above its threshold, and is active low when the burst threshold during sleep periods for better transient internal clamp on the C response. Driving the V T pin is below its clamp level and C pin to ground will disable switch- high impedance when the clamp is active. The PG pin has ing and also place the LT1976 into sleep mode. a typical sink capability of 200μA. See the Power Good
FB (Pin 12):
The feedback pin is used to determine the section in Applications Information for details. output voltage using an external voltage divider from the output that generates 1.25V at the FB pin . When the FB pin drops below 0.9V, switching frequency is reduced, the SYNC function is disabled and output ramp rate control is enabled via the CSS pin. See the Feedback section in Applications Information for details. 1976bfg 9