Datasheet LT3724 (Analog Devices) - 6

LT3724
PIN FUNCTIONS VIN (Pin 1):
The VIN pin is the main supply pin and should
VC (Pin 7):
The VC pin is the output of the error amplifier be decoupled to SGND with a low ESR capacitor located whose voltage corresponds to the maximum (peak) switch close to the pin. current per oscillator cycle. The error amplifier is typically
NC (Pin 2):
No Connection. configured as an integrator circuit by connecting an RC network from the VC pin to SGND. This circuit creates the
SHDN (Pin 3):
The SHDN pin has a precision IC enable dominant pole for the converter regulation control loop. threshold of 1.35V (rising) with 120mV of hysteresis. It is Specific integrator characteristics can be configured to used to implement an undervoltage lockout (UVLO) circuit. optimize transient response. Connecting a 100pF or greater See Application Information section for implementing a high frequency bypass capacitor from this pin to ground UVLO function. When the SHDN pin is pulled below a is recommended. When Burst Mode operation is enabled transistor VBE (0.7V), a low current shutdown mode is (see Pin 5 description), an internal low impedance clamp entered, all internal circuitry is disabled and the VIN sup- on the VC pin is set at 100mV below the burst threshold, ply current is reduced to approximately 10µA. Typical which limits the negative excursion of the pin voltage. pin input bias current is <10µA and the pin is internally Therefore, this pin cannot be pulled low with a low imped- clamped to 6V. ance source. If the VC pin must be externally manipulated,
C
do so through a 1kΩ series resistance.
SS (Pin 4):
The soft-start pin is used to program the sup- ply soft-start function. The pin is connected to VOUT via a
SGND (Pin 8, 17):
The SGND pin is the low noise ground ceramic capacitor (CSS) and 200kΩ series resistor. During reference. It should be connected to the –VOUT side of the start-up, the supply output voltage slew rate is controlled output capacitors. Careful layout of the PCB is necessary to produce a 2µA average current through the soft-start to keep high currents away from this SGND connection. coupling capacitor. Use the following formula to calculate See the Application Information section for helpful hints CSS for a given output voltage slew rate: on PCB layout of grounds. CSS = 2µA(tSS/VOUT)
SENSE– (Pin 9):
The SENSE– pin is the negative input for See the application section for more information on setting the current sense amplifier and is connected to the VOUT the rise time of the output voltage during start-up. Shorting side of the sense resistor for step-down applications. The this pin to SGND disables the soft-start function. sensed inductor current limit is set to 150mV across the SENSE inputs.
BURST_EN (Pin 5):
The BURST_EN pin is used to enable or disable Burst Mode operation. Connect the BURST_EN
SENSE+ (Pin 10):
The SENSE+ pin is the positive input for pin to ground to enable the burst mode function. Connect the current sense amplifier and is connected to the induc- the pin to V tor side of the sense resistor for step-down applications. CC to disable the burst mode function. The sensed inductor current limit is set to 150mV across
VFB (Pin 6):
The output voltage feedback pin, VFB, is the SENSE inputs. externally connected to the supply output voltage via a resistive divider. The V
PGND (Pin 11):
The PGND pin is the high-current ground FB pin is internally connected to the inverting input of the error amplifier. In regulation, reference for internal low side switch and the VCC regulator V circuit. Connect the pin directly to the negative terminal of FB is 1.231V. the VCC decoupling capacitor. See the Application Informa- tion section for helpful hints on PCB layout of grounds. 3724fd 6