Datasheet LT3437 (Analog Devices) - 10

LT3437
W BLOCK DIAGRA
VIN INTERNAL REF SLOPE 2.4V COMP UNDERVOLTAGE LOCKOUT Σ + BIAS THERMAL 200kHz SHUTDOWN CURRENT OSCILLATOR COMP SYNC – BOOST ANTISLOPE SHDN COMP + R SHDN SWITCH DRIVER COMP Q LATCH CIRCUITRY – S SW 1.3V CSS BURST MODE SOFT-START DETECT FOLDBACK VC DETECT CLAMP FB – ERROR AMP GND 1.25V + VC PGND 3437 BD
Figure 1. LT3437 Block Diagram
The LT3437 is a constant frequency, current mode buck power from the VIN pin, but if the BIAS pin is connected to converter. This means that there is an internal clock and two an external voltage higher than 2.7V, bias power will be feedback loops that control the duty cycle of the power drawn from the external source (typically the regulated switch. In addition to the normal error amplifier, there is a output voltage). This improves efficiency. current sense amplifier that monitors switch current on a High switch efficiency is attained by using the BOOST pin cycle-by-cycle basis. A switch cycle starts with an oscilla- to provide a voltage to the switch driver which is higher tor pulse which sets the RS latch to turn the switch on. When than the input voltage, allowing the switch to be saturated. switch current reaches a level set by the current compara- This boosted voltage is generated with an external capaci- tor, the latch is reset and the switch turns off. Output volt- tor and diode. age control is obtained by using the output of the error amplifier to set the switch current trip point. This technique To further optimize efficiency, the LT3437 automatically means that the error amplifier commands current to be switches to Burst Mode operation in light load situations. In delivered to the output rather than voltage. A voltage fed Burst Mode operation, all circuitry associated with control- system will have low phase shift up to the resonant fre- ling the output switch is shut down, reducing the input quency of the inductor and output capacitor, then an abrupt supply current to 45µA and bias input current to 110µA. 180° shift will occur. The current fed system will have 90° If lower output ripple is desired over light load efficiency, phase shift at a much lower frequency, but will not have the Burst Mode operation can be defeated by setting the SYNC additional 90° shift until well beyond the LC resonant fre- pin voltage greater than 2V. A logic-level low on the SHDN quency. This makes it much easier to frequency compen- pin disables the IC and reduces input supply current to less sate the feedback loop and gives much quicker transient than 1µA. External synchronization can be implemented response and line rejection. by driving the SYNC pin with logic-level inputs. Most of the circuitry of the LT3437 operates from an internal 2.4V bias line. The bias regulator normally draws 3437fc 10