Datasheet LT3844 (Analog Devices) - 6

HerstellerAnalog Devices
BeschreibungHigh Voltage, Current Mode Switching Regulator Controller with Programmable Operating Frequency
Seiten / Seite26 / 6 — pin FuncTions. VIN (Pin 1):. SHDN (Pin 2):. SYNC (Pin 7):. SET (Pin 8):. …
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DokumentenspracheEnglisch

pin FuncTions. VIN (Pin 1):. SHDN (Pin 2):. SYNC (Pin 7):. SET (Pin 8):. CSS (Pin 3):. SGND (Pin 9, 17):. BURST_EN (Pin 4):

pin FuncTions VIN (Pin 1): SHDN (Pin 2): SYNC (Pin 7): SET (Pin 8): CSS (Pin 3): SGND (Pin 9, 17): BURST_EN (Pin 4):

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LT3844
pin FuncTions VIN (Pin 1):
The VIN pin is the main supply pin and should voltage. Therefore, this pin cannot be pulled low with a be decoupled to SGND with a low ESR capacitor located low impedance source. If the VC pin must be externally close to the pin. manipulated, do so through a 1k series resistance.
SHDN (Pin 2):
The SHDN pin has a precision IC enable
SYNC (Pin 7):
The SYNC pin provides an external clock threshold of 1.35V (rising) with 120mV of hysteresis. It is input for synchronization of the internal oscillator. RSET used to implement an undervoltage lockout (UVLO) circuit. is set such that the internal oscillator frequency is 10% See Applications Information section for implementing to 25% below the external clock frequency. If unused the a UVLO function. When the SHDN pin is pulled below SYNC pin is connected to SGND. For more information see a transistor VBE (0.7V), a low current shutdown mode “Oscillator Sync” in the Applications Information section is entered, all internal circuitry is disabled and the VIN of this data sheet. supply current is reduced to approximately 9µA. Typical
f
pin input bias current is <10µA and the pin is internally
SET (Pin 8):
The fSET pin programs the oscillator frequency with an external resistor, R clamped to 6V. SET . The resistor is required even when supplying external sync clock signal. See the
CSS (Pin 3):
The soft-start pin is used to program the Applications Information section for resistor value selec- supply soft-start function. Use the following formula to tion details. calculate CSS for a given output voltage slew rate:
SGND (Pin 9, 17):
The SGND pin is the low noise ground CSS = 2µA(tSS/1.231V) reference. It should be connected to the –VOUT side of the output capacitors. Careful layout of the PCB is necessary The pin should be left unconnected when not using the to keep high currents away from this SGND connection. soft-start function. See the Applications Information section for helpful hints
BURST_EN (Pin 4):
The BURST_EN pin is used to enable on PCB layout of grounds. or disable Burst Mode operation. Connect the BURST_EN
SENSE– (Pin 10):
The SENSE– pin is the negative input for pin to ground to enable the burst mode function. Connect the current sense amplifier and is connected to the V the pin to V OUT FB or VCC to disable the Burst Mode function. side of the sense resistor for step-down applications. The
VFB (Pin 5):
The output voltage feedback pin, VFB, is exter- sensed inductor current limit is set to 100mV across the nally connected to the supply output voltage via a resistive SENSE inputs. divider. The VFB pin is internally connected to the inverting
SENSE+ (Pin 11):
The SENSE+ pin is the positive input for input of the error amplifier. In regulation, VFB is 1.231V. the current sense amplifier and is connected to the induc-
VC (Pin 6):
The VC pin is the output of the error amplifier tor side of the sense resistor for step-down applications. whose voltage corresponds to the maximum (peak) switch The sensed inductor current limit is set to 100mV across current per oscillator cycle. The error amplifier is typically the SENSE inputs. configured as an integrator circuit by connecting an RC
PGND (Pin 12):
The PGND pin is the high current ground network from the VC pin to SGND. This circuit creates the reference for internal low side switch and the V dominant pole for the converter regulation control loop. CC regulator circuit. Connect the pin directly to the negative terminal of Specific integrator characteristics can be configured to the V optimize transient response. When Burst Mode operation CC decoupling capacitor. See the Applications Informa- tion section for helpful hints on PCB layout of grounds. is enabled (see Pin 4 description), an internal low imped- ance clamp on the VC pin is set at 100mV below the burst threshold, which limits the negative excursion of the pin 3844fc 6 For more information www.linear.com/LT3844 Document Outline Features Applications Typical Application Description Absolute Maximum Ratings Order Information Electrical Characteristics Pin Configuration Typical Performance Characteristics Pin Functions Functional Diagram Operation Applications Information Typical Applications Package Description Revision History Typical Application Related Parts