Datasheet LT3641 (Analog Devices) - 10
| Hersteller | Analog Devices |
| Beschreibung | Dual Monolithic Buck Regulator with Power-On Reset and Watchdog Timer |
| Seiten / Seite | 28 / 10 — TIMING DIAGRAMS. Power-On Reset Timing. Watchdog Timing. OPERATION. Buck … |
| Dateiformat / Größe | PDF / 452 Kb |
| Dokumentensprache | Englisch |
TIMING DIAGRAMS. Power-On Reset Timing. Watchdog Timing. OPERATION. Buck Regulators
Modelllinie für dieses Datenblatt
Textversion des Dokuments
LT3641
TIMING DIAGRAMS Power-On Reset Timing
FB t t UV RST RST
Watchdog Timing
WDI WDO t < tWDU tDLY tWDU t < tWDL tRST tWDL < t < tWDU tRST 3641 TD
OPERATION
The LT3641 is a dual channel, constant-frequency, current An active clamp (not shown) on the VC1 node provides mode monolithic buck switching regulator with power-on peak current limit. A DA pin current comparator extends reset and watchdog timer. Both channels are synchronized the oscillator cycle until the catch diode current is below to a single oscillator with frequency set by RT. Operation the valley current limit. Both the peak and valley current can be best understood by referring to the Block Diagram. limits help to control the inductor current in fault condi- tions such as shorted output with high VIN. Both current
Buck Regulators
limits are reduced when the voltage at the FB1 pin is below The high voltage channel is a nonsynchronous buck 0.2V. This current foldback helps to control the inductor regulator that operates from the V current during start-up and overload. IN pin. The start of each oscillator cycle sets an SR latch and turns on the internal The NPN power switch driver operates from either the VIN NPN power switch. An amplifi er and comparator monitor pin or the BST pin. An external capacitor and diode are the current fl owing between the VIN and SW1 pins, turning used to generate a voltage between the BST and SW pins. the switch off when this current reaches a level determined During the power-up of the LT3641, an internal 5mA current by the voltage at VC1 node. An error amplifi er measures source charges the external BST capacitor. The regulator the output voltage through an external resistor divider tied starts switching when the (BST-SW) voltage reaches the to the FB1 pin and servos the VC1 node. The reference 2V threshold. The internal NPN power switch can be fully of the error amplifi er is determined by the lower of the saturated for effi cient operation when the (BST-SW) voltage internal reference and the voltage at the SS1 pin. If the error is between 2.3V and 5.5V. amplifi er’s output increases, more current is delivered to The low voltage channel is a synchronous buck regulator the output; if it decreases, less current is delivered. that operates from the VIN2 pin. It starts switching only 3641fa 10
TIMING DIAGRAMS Power-On Reset Timing
FB t t UV RST RST
Watchdog Timing
WDI WDO t < tWDU tDLY tWDU t < tWDL tRST tWDL < t < tWDU tRST 3641 TD
OPERATION
The LT3641 is a dual channel, constant-frequency, current An active clamp (not shown) on the VC1 node provides mode monolithic buck switching regulator with power-on peak current limit. A DA pin current comparator extends reset and watchdog timer. Both channels are synchronized the oscillator cycle until the catch diode current is below to a single oscillator with frequency set by RT. Operation the valley current limit. Both the peak and valley current can be best understood by referring to the Block Diagram. limits help to control the inductor current in fault condi- tions such as shorted output with high VIN. Both current
Buck Regulators
limits are reduced when the voltage at the FB1 pin is below The high voltage channel is a nonsynchronous buck 0.2V. This current foldback helps to control the inductor regulator that operates from the V current during start-up and overload. IN pin. The start of each oscillator cycle sets an SR latch and turns on the internal The NPN power switch driver operates from either the VIN NPN power switch. An amplifi er and comparator monitor pin or the BST pin. An external capacitor and diode are the current fl owing between the VIN and SW1 pins, turning used to generate a voltage between the BST and SW pins. the switch off when this current reaches a level determined During the power-up of the LT3641, an internal 5mA current by the voltage at VC1 node. An error amplifi er measures source charges the external BST capacitor. The regulator the output voltage through an external resistor divider tied starts switching when the (BST-SW) voltage reaches the to the FB1 pin and servos the VC1 node. The reference 2V threshold. The internal NPN power switch can be fully of the error amplifi er is determined by the lower of the saturated for effi cient operation when the (BST-SW) voltage internal reference and the voltage at the SS1 pin. If the error is between 2.3V and 5.5V. amplifi er’s output increases, more current is delivered to The low voltage channel is a synchronous buck regulator the output; if it decreases, less current is delivered. that operates from the VIN2 pin. It starts switching only 3641fa 10