Datasheet LTC3646, LTC3646-1 (Analog Devices) - 9
| Hersteller | Analog Devices |
| Beschreibung | 40V, 1A Synchronous Step-Down Converter |
| Seiten / Seite | 28 / 9 — OPERATION. Main Control Loop. Power Good Status Output |
| Dateiformat / Größe | PDF / 596 Kb |
| Dokumentensprache | Englisch |
OPERATION. Main Control Loop. Power Good Status Output
Modelllinie für dieses Datenblatt
- LTC3646EDE#PBF LTC3646EDE#TRPBF LTC3646EDE-1#PBF LTC3646EDE-1#TRPBF LTC3646EMSE#PBF LTC3646EMSE#TRPBF LTC3646EMSE-1#PBF LTC3646EMSE-1#TRPBF LTC3646HDE#PBF LTC3646HDE#TRPBF LTC3646HDE-1#PBF LTC3646HDE-1#TRPBF LTC3646HMSE#PBF LTC3646HMSE#TRPBF LTC3646HMSE-1#PBF LTC3646HMSE-1#TRPBF LTC3646IDE#PBF LTC3646IDE#TRPBF LTC3646IDE-1#PBF LTC3646IDE-1#TRPBF LTC3646IMSE#PBF LTC3646IMSE#TRPBF LTC3646IMSE-1#PBF LTC3646IMSE-1#TRPBF
Textversion des Dokuments
LTC3646/LTC3646-1
OPERATION
The LTC3646 and LTC3646-1 are current mode, monolithic, then shuts off the bottom power MOSFET and places the synchronous, step-down regulators capable of 40V input part into a low quiescent current sleep state, resulting in operation, and extremely high step down ratios while main- discontinuous operation and increased efficiency at low taining constant frequency. (Both will be referred to as the load currents. Both power MOSFETs will remain off with LTC3646 except as specifically noted.) Part operation is the part in sleep and the output capacitor supplying the enabled by raising the voltage of the RUN pin above 1.21V. load current until the ITH voltage rises sufficiently to initiate another cycle. Discontinuous operation is disabled by tying
Main Control Loop
the MODE/SYNC pin to ground, placing the LTC3646 into In normal operation a switching cycle is initiated by a forced continuous mode. During forced continuous mode signal from the inductor valley current comparator (I operation, synchronous operation occurs regardless of CMP in the Block Diagram). The top power MOSFET is turned the output load current, and the inductor current trough on, and a timer is simultaneously started in the on-time levels are allowed to become negative. controller. The on-time controller computes the correct on The operating frequency is determined by the value of the time (subject to tON(MIN)) based on the desired switching RRT resistor, which programs the current for the internal frequency fO, and step-down ratio VON/VIN, according to the oscil ator. An internal phase-locked loop adjusts the switch- formula shown in the Block Diagram. In a typical applica- ing regulator on-time so that the switching frequency tion, the VON pin should be connected to the output voltage, matches the programmed frequency, subject to tON and VOUT. When the timer expires, the top power MOSFET is tOFF time constraints shown in the Electrical Characteristics turned off and the bottom power MOSFET is turned on table. Alternatively, the RT pin can be connected to the until the current comparator (ICMP) trips, restarting the INTVCC pin which causes the internal oscillator to run at timer and initiating the next cycle. The inductor current the default frequency of 2.25MHz. is monitored by sensing the voltage drop across the SW and PGND nodes of the bottom power MOSFET. The volt- A clock signal can be applied to the MODE/SYNC pin to age at the ITH node sets the I synchronize the switching frequency to an external source. CMP comparator threshold corresponding to the inductor valley current. The error When operating in this configuration, connect a resistor to amplifier (EA) adjusts the ITH voltage by comparing an the RT pin with a value corresponding to the applied clock internal 0.6V reference voltage to the feedback signal, frequency. With an external clock supplied to the MODE/ V SYNC pin, the part will operate in forced continuous mode. FB, derived from the output voltage. If, for example, the load current increases, the output voltage will decrease
Power Good Status Output
relative to the 0.6V reference. The ITH voltage will rise until the average inductor current increases to match the The PGOOD open-drain output will be pulled low if the load current. regulator output exits the VPGOOD window around the regulation point. This condition is released once regula- At low load currents, the inductor current can drop to tion within the specified window is achieved. To prevent zero or become negative. If the LTC3646 is configured for unwanted PGOOD glitches during transients or dynamic Burst Mode operation, this inductor current condition is V detected by the current reversal comparator (I OUT changes, the LTC3646 PGOOD falling edge includes REV) which a filter time of approximately 70 clock cycles. 36461fc For more information www.linear.com/LTC3646 9 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Typical Performance Characteristics Pin Functions Functional Block Diagram Operation Applications Information Typical Applications Typical Application Related Parts
OPERATION
The LTC3646 and LTC3646-1 are current mode, monolithic, then shuts off the bottom power MOSFET and places the synchronous, step-down regulators capable of 40V input part into a low quiescent current sleep state, resulting in operation, and extremely high step down ratios while main- discontinuous operation and increased efficiency at low taining constant frequency. (Both will be referred to as the load currents. Both power MOSFETs will remain off with LTC3646 except as specifically noted.) Part operation is the part in sleep and the output capacitor supplying the enabled by raising the voltage of the RUN pin above 1.21V. load current until the ITH voltage rises sufficiently to initiate another cycle. Discontinuous operation is disabled by tying
Main Control Loop
the MODE/SYNC pin to ground, placing the LTC3646 into In normal operation a switching cycle is initiated by a forced continuous mode. During forced continuous mode signal from the inductor valley current comparator (I operation, synchronous operation occurs regardless of CMP in the Block Diagram). The top power MOSFET is turned the output load current, and the inductor current trough on, and a timer is simultaneously started in the on-time levels are allowed to become negative. controller. The on-time controller computes the correct on The operating frequency is determined by the value of the time (subject to tON(MIN)) based on the desired switching RRT resistor, which programs the current for the internal frequency fO, and step-down ratio VON/VIN, according to the oscil ator. An internal phase-locked loop adjusts the switch- formula shown in the Block Diagram. In a typical applica- ing regulator on-time so that the switching frequency tion, the VON pin should be connected to the output voltage, matches the programmed frequency, subject to tON and VOUT. When the timer expires, the top power MOSFET is tOFF time constraints shown in the Electrical Characteristics turned off and the bottom power MOSFET is turned on table. Alternatively, the RT pin can be connected to the until the current comparator (ICMP) trips, restarting the INTVCC pin which causes the internal oscillator to run at timer and initiating the next cycle. The inductor current the default frequency of 2.25MHz. is monitored by sensing the voltage drop across the SW and PGND nodes of the bottom power MOSFET. The volt- A clock signal can be applied to the MODE/SYNC pin to age at the ITH node sets the I synchronize the switching frequency to an external source. CMP comparator threshold corresponding to the inductor valley current. The error When operating in this configuration, connect a resistor to amplifier (EA) adjusts the ITH voltage by comparing an the RT pin with a value corresponding to the applied clock internal 0.6V reference voltage to the feedback signal, frequency. With an external clock supplied to the MODE/ V SYNC pin, the part will operate in forced continuous mode. FB, derived from the output voltage. If, for example, the load current increases, the output voltage will decrease
Power Good Status Output
relative to the 0.6V reference. The ITH voltage will rise until the average inductor current increases to match the The PGOOD open-drain output will be pulled low if the load current. regulator output exits the VPGOOD window around the regulation point. This condition is released once regula- At low load currents, the inductor current can drop to tion within the specified window is achieved. To prevent zero or become negative. If the LTC3646 is configured for unwanted PGOOD glitches during transients or dynamic Burst Mode operation, this inductor current condition is V detected by the current reversal comparator (I OUT changes, the LTC3646 PGOOD falling edge includes REV) which a filter time of approximately 70 clock cycles. 36461fc For more information www.linear.com/LTC3646 9 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Typical Performance Characteristics Pin Functions Functional Block Diagram Operation Applications Information Typical Applications Typical Application Related Parts