Datasheet LTC3877 (Analog Devices) - 10
| Hersteller | Analog Devices |
| Beschreibung | Dual Phase Step-Down Synchronous Controller with VID Output Voltage Programming and Low Value DCR Sensing |
| Seiten / Seite | 46 / 10 — pin FuncTions TK/SS1, TK/SS2 (Pin 2, Pin 9):. PHASMD (Pin 19):. CLKOUT … |
| Dateiformat / Größe | PDF / 1.1 Mb |
| Dokumentensprache | Englisch |
pin FuncTions TK/SS1, TK/SS2 (Pin 2, Pin 9):. PHASMD (Pin 19):. CLKOUT (Pin 22):. ITEMP (Pin 42):
Modelllinie für dieses Datenblatt
Textversion des Dokuments
LTC3877
pin FuncTions TK/SS1, TK/SS2 (Pin 2, Pin 9):
Output Voltage Tracking
PHASMD (Pin 19):
Phase Program Pin. This pin can be and Soft Start Inputs. When one channel is configured to tied to SGND, INTVCC or left floating. It determines the be the master, a capacitor to ground at this pin sets the relative phases between the internal controllers as well ramp rate for the master channel’s output voltage. When as the phasing of the CLKOUT signal. See Table 1 in the the channel is configured to be the slave, the feedback Operation section for detail. voltage of the master channel is reproduced by a resistor
CLKOUT (Pin 22):
Clock Output Pin. Clock output with divider and applied to this pin. Internal soft start currents phase changeable by PHASMD to enable usage of multiple of 1.25µA charge these pins. LTC3877s in PolyPhase systems. Signal swing is from
ITEMP (Pin 42):
Input to the Temperature Sensing INTVCC to ground. Comparator. This pin can be programmed to compensate
BOOST1, BOOST2 (Pin 31, Pin 25):
Boosted Floating the temperature coefficient of the inductor DCR. When Driver Supplies. The (+) terminal of the bootstrap capaci- CHL_SEL is asserted, the voltage on this pin can be used tors connect to these pins. These pins swing from a diode to compensate both channels temperature. When CHL_SEL voltage drop below INTV is grounded, the voltage on this pin only compensates CC up to VIN + INTVCC. channel 1's current limit for temperature. Connect this
TG1, TG2 (Pin 32, Pin 24):
Top Gate Driver Outputs. These pin to an external NTC resistor network placed near the are the outputs of floating drivers with a voltage swing appropriate inductors. Floating this pin disables the DCR equal to INTVCC superimposed on the switch node voltage. temperature compensation function.
SW1, SW2 (Pin 33, Pin 23):
Switch Node Connections to
PGOOD1, PGOOD2 (Pin 20, Pin 21):
Power Good Indicator Inductors. Voltage swings at these pins are from a Schottky Output for Each Channel. Open drain logic that is pulled to diode (external) voltage drop below ground to VIN. ground when the respective channel’s output exceeds its
BG1, BG2 (Pin 30, Pin 26):
Bottom Gate Driver Outputs. ±10% regulation window, after the internal 50µs power These pins drive the gates of the bottom N-Channel MOS- bad mask timer expires. During a VID transition, PGOOD FETs between PGND and INTV is blanked for 235µs. CC.
V MODE/PLLIN (Pin 18):
Force Continuous Mode, Burst
IN (Pin 29):
Main Input Supply. Bypass this pin to PGND with a capacitor (0.1µF to 1µF). Mode or Pulse Skip Mode Selection Pin and External Syn- chronization Input to Phase Detector Pin. Connect this pin
INTVCC (Pin 28):
Internal 5.5V Regulator Output. The to SGND to force the IC into continuous mode of operation. control circuits are powered from this voltage. Bypass this Connect to INTV pin to PGND with a minimum of 4.7µF low ESR tantalum CC to enable pulse skip mode of operation. Leave the pin floating to enable Burst Mode operation. A or ceramic capacitor. clock on the pin will force the IC into continuous mode
EXTVCC (Pin 27):
External Power Input to Internal Switch of operation and synchronize the internal oscillator with Connected to INTVCC. The internal switch closes and sup- the clock on this pin. The PLL compensation network is plies the IC power, bypassing the internal low dropout integrated into the IC. regulator, whenever EXTVCC is higher than 4.7V. Do not
FREQ (Pin 17):
Oscillator Frequency Control Input. There exceed 6V on this pin. is a precision 10µA current flowing out of this pin. A resis-
SGND/PGND (Exposed Pad Pin 45):
Signal/Power Ground tor to ground sets a voltage which in turn programs the Pin. Connect this pin closely to the sources of the bottom frequency. Alternatively, this pin can be driven with a DC N-channel MOSFETs and the negative terminals of the voltage to vary the frequency of the internal oscillator. VIN and INTVCC bypassing capacitors. All small-signal components and compensation components should also connect to this ground. 3877f 10 For more information www.linear.com/LTC3877
pin FuncTions TK/SS1, TK/SS2 (Pin 2, Pin 9):
Output Voltage Tracking
PHASMD (Pin 19):
Phase Program Pin. This pin can be and Soft Start Inputs. When one channel is configured to tied to SGND, INTVCC or left floating. It determines the be the master, a capacitor to ground at this pin sets the relative phases between the internal controllers as well ramp rate for the master channel’s output voltage. When as the phasing of the CLKOUT signal. See Table 1 in the the channel is configured to be the slave, the feedback Operation section for detail. voltage of the master channel is reproduced by a resistor
CLKOUT (Pin 22):
Clock Output Pin. Clock output with divider and applied to this pin. Internal soft start currents phase changeable by PHASMD to enable usage of multiple of 1.25µA charge these pins. LTC3877s in PolyPhase systems. Signal swing is from
ITEMP (Pin 42):
Input to the Temperature Sensing INTVCC to ground. Comparator. This pin can be programmed to compensate
BOOST1, BOOST2 (Pin 31, Pin 25):
Boosted Floating the temperature coefficient of the inductor DCR. When Driver Supplies. The (+) terminal of the bootstrap capaci- CHL_SEL is asserted, the voltage on this pin can be used tors connect to these pins. These pins swing from a diode to compensate both channels temperature. When CHL_SEL voltage drop below INTV is grounded, the voltage on this pin only compensates CC up to VIN + INTVCC. channel 1's current limit for temperature. Connect this
TG1, TG2 (Pin 32, Pin 24):
Top Gate Driver Outputs. These pin to an external NTC resistor network placed near the are the outputs of floating drivers with a voltage swing appropriate inductors. Floating this pin disables the DCR equal to INTVCC superimposed on the switch node voltage. temperature compensation function.
SW1, SW2 (Pin 33, Pin 23):
Switch Node Connections to
PGOOD1, PGOOD2 (Pin 20, Pin 21):
Power Good Indicator Inductors. Voltage swings at these pins are from a Schottky Output for Each Channel. Open drain logic that is pulled to diode (external) voltage drop below ground to VIN. ground when the respective channel’s output exceeds its
BG1, BG2 (Pin 30, Pin 26):
Bottom Gate Driver Outputs. ±10% regulation window, after the internal 50µs power These pins drive the gates of the bottom N-Channel MOS- bad mask timer expires. During a VID transition, PGOOD FETs between PGND and INTV is blanked for 235µs. CC.
V MODE/PLLIN (Pin 18):
Force Continuous Mode, Burst
IN (Pin 29):
Main Input Supply. Bypass this pin to PGND with a capacitor (0.1µF to 1µF). Mode or Pulse Skip Mode Selection Pin and External Syn- chronization Input to Phase Detector Pin. Connect this pin
INTVCC (Pin 28):
Internal 5.5V Regulator Output. The to SGND to force the IC into continuous mode of operation. control circuits are powered from this voltage. Bypass this Connect to INTV pin to PGND with a minimum of 4.7µF low ESR tantalum CC to enable pulse skip mode of operation. Leave the pin floating to enable Burst Mode operation. A or ceramic capacitor. clock on the pin will force the IC into continuous mode
EXTVCC (Pin 27):
External Power Input to Internal Switch of operation and synchronize the internal oscillator with Connected to INTVCC. The internal switch closes and sup- the clock on this pin. The PLL compensation network is plies the IC power, bypassing the internal low dropout integrated into the IC. regulator, whenever EXTVCC is higher than 4.7V. Do not
FREQ (Pin 17):
Oscillator Frequency Control Input. There exceed 6V on this pin. is a precision 10µA current flowing out of this pin. A resis-
SGND/PGND (Exposed Pad Pin 45):
Signal/Power Ground tor to ground sets a voltage which in turn programs the Pin. Connect this pin closely to the sources of the bottom frequency. Alternatively, this pin can be driven with a DC N-channel MOSFETs and the negative terminals of the voltage to vary the frequency of the internal oscillator. VIN and INTVCC bypassing capacitors. All small-signal components and compensation components should also connect to this ground. 3877f 10 For more information www.linear.com/LTC3877