Datasheet ADP2360 (Analog Devices) - 10

ADP2360 Data Sheet THEORY OF OPERATION VIN CIN VIN 8 VREG BG UVLO UVLO 0µA TO BAND GAP TSD TSD 0.8V 5µA ITH VREG VREG 3 g R M ITH VITH IPEAK VREG COMPARATOR ADJUSTABLE OUTPUT ADP2360 VOLTAGE 1µA I V PEAK OUT SS CONTROL 5 LEVEL R1 FB C SHIFT SS 4 SW L1 R2 V 7 OUT COUT FEEDBACK CONTROL LOGIC COMPARATOR 0.8V FIXED OUTPUT VOLTAGE ZERO CROSSING PGND DETECTOR FB 6 UVLO COMPARATOR 4 VOUT TSD R1 VIN RPG R2 V PG EN PG_RISING 2 1 POWER GOOD ENABLE COMPARATOR VEN_RISING 9 AGND NOTES
21
1. THE PORTIONS IN THE DASHED BOXES DISPLAY THE DIFFERENCE OF THE FUNCTIONALITY OF PIN 4
0 44-
FOR THE ADJUSTABLE AND FIXED OUTPUT VOLTAGES.
139 Figure 21. Block Diagram
OVERVIEW
When the PMOS turns off, the NMOS turns on, reducing the The ADP2360 is a high efficiency, high input voltage, DCM energy stored in the inductor until the inductor current reaches synchronous, step-down, dc-to-dc switching regulator. zero. At this point, the NMOS also turns off. The ADP2360 uses a single-pulse PFM architecture with adjustable When both the NMOS and PMOS are off, the ADP2360 enters I into sleep mode. During this phase of operation, the stored energy PEAK control to adjust the frequency variation within the application and to minimize the input and output ripple. in COUT delivers the load current, and thus VOUT and VFB decrease. When VFB drops below the VFB_FALLING threshold, another The ADP2360 further offers a power-good (PG) pin with an switching cycle begins. open-drain output signal to indicate when the output voltage is stable. Other key features include 100% duty cycle operation,
IPEAK
precision enable control, external soft start control, undervoltage
I tSLEEP L
lockout, and thermal shutdown.
CONTROL SCHEME
The ADP2360 uses a single-pulse, peak current PFM control
PMOS
scheme. A switching cycle is started when the FB pin voltage, VFB, is less than the VFB_FALLING threshold, and the PMOS is turned
NMOS
on. While the PMOS is on, the current through the inductor increases to charge the output capacitor (COUT) and store energy
FBVFB_FALLING
in the inductor. The current through the inductor continues to increase until it reaches the IPEAK programmed via the ITH pin. When I
V
PEAK is reached, or if the VFB voltage rises above VFB_RISING,
OUT
-022 the PMOS turns off. 44 139 Figure 22. Control Scheme Typical Waveforms Rev. A | Page 10 of 15 Document Outline FEATURES APPLICATIONS TYPICAL APPLICATION CIRCUIT GENERAL DESCRIPTION REVISION HISTORY SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION OVERVIEW CONTROL SCHEME 100% Duty Cycle Adjustable Peak Current Threshold (ITH) DEVICE FEATURES Fixed and Adjustable Output Models Shutdown/Precision Enable Soft Start Thermal Shutdown (TSD) Undervoltage Lockout (UVLO) Power Good APPLICATIONS INFORMATION SETTING THE OUTPUT VOLTAGE INPUT CAPACITOR SELECTION ESTIMATING THE SWITCHING FREQUENCY SETTING THE PEAK INDUCTOR CURRENT INDUCTOR SELECTION OUTPUT CAPACITOR SELECTION DESIGN OPTIMIZATION RECOMMENDED COMPONENTS PCB LAYOUT CONSIDERATIONS OUTLINE DIMENSIONS ORDERING GUIDE