Datasheet LT1457 (Analog Devices) - 7

HerstellerAnalog Devices
BeschreibungDual, Precision JFET Input Op Amp
Seiten / Seite8 / 7 — APPLICATIONS INFORMATION. High Speed Operation
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DokumentenspracheEnglisch

APPLICATIONS INFORMATION. High Speed Operation

APPLICATIONS INFORMATION High Speed Operation

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LT1457
U U W U APPLICATIONS INFORMATION High Speed Operation
When the feedback around the op amp is resisitive (R C F), a F pole will be created with RF, the source resistance and capacitance (RS, CS), and the amplifier input capacitance RF (CIN ≈ 4pF). In low closed loop gain configurations and with RS and RF in the kilohm range, this pole can create – excess phase shift and even oscillation on high speed CIN OUTPUT amplifiers. Because the LT1457’s phase margin is very R C S S + high, this problem is minimal. However, a small capacitor LT1457 AI04 (CF) in parallel with RF eliminates this problem. With RS(CS + CIN) = RFCF, the effect of the feedback pole is completely removed.
U PACKAGE DESCRIPTION Dimension in inches (millimeters) unless otherwise noted. N8 Package 8-Lead Plastic DIP
0.300 – 0.320 0.045 – 0.065 0.130 ± 0.005 0.400 (7.620 – 8.128) (1.143 – 1.651) (3.302 ± 0.127) (10.160) MAX 8 7 6 5 0.065 (1.651) 0.009 – 0.015 TYP 0.125 0.250 ± 0.010 (0.229 – 0.381) (3.175) 0.020 (6.350 ± 0.254) +0.025 0.045 ± 0.015 MIN (0.508) 0.325 –0.015 MIN (1.143 ± 0.381) +0.635 8.255 1 2 3 4 ( ) –0.381 0.100 ± 0.010 0.018 ± 0.003 (2.540 ± 0.254) (0.457 ± 0.076) N8 0392
S8 Package 8-Lead Plastic SOIC
0.189 – 0.197 (4.801 – 5.004) 0.010 – 0.020 8 7 6 5 × 45° 0.053 – 0.069 (0.254 – 0.508) (1.346 – 1.752) 0.008 – 0.010 0.004 – 0.010 (0.203 – 0.254) (0.101 – 0.254) 0.228 – 0.244 0.150 – 0.157 0.016 – 0.050 (5.791 – 6.197) (3.810 – 3.988) 0°– 8° TYP 0.014 – 0.019 0.050 0.406 – 1.270 (0.355 – 0.483) (1.270) BSC 1 2 3 4 SO8 0392 Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 7