Datasheet ADE7759 (Analog Devices) - 5

ADE7759 (AV TIMING CHARACTERISTICS1, 2 DD = DVDD = 5 V 5%, AGND = DGND = 0 V, On-Chip Reference, CLKIN = 3.579545 MHz XTAL, TMIN to TMAX = –40 C to +85 C, unless otherwise noted.) Parameter A, B Versions Unit Test Conditions/Comments
Write Timing t1 20 ns (min) CS Falling Edge to First SCLK Falling Edge t2 150 ns (min) SCLK Logic High Pulsewidth t3 150 ns (min) SCLK Logic Low Pulsewidth t4 10 ns (min) Valid Data Setup Time before Falling Edge of SCLK t5 5 ns (min) Data Hold Time after SCLK Falling Edge t6 6.4 ms (min) Minimum Time between the End of Data Byte Transfers t7 4 ms (min) Minimum Time between Byte Transfers during a Serial Write t8 100 ns (min) CS Hold Time after SCLK Falling Edge Read Timing t9 4 ms (min) Minimum Time between Read Command (i.e., a Write to Communications Register) and Data Read t10 4 ms (min) Minimum Time between Data Byte Transfers during a Multibyte Read t 3 11 30 ns (min) Data Access Time after SCLK Rising Edge following a Write to the Communica- tions Register t 4 12 100 ns (max) Bus Relinquish Time after Falling Edge of SCLK 10 ns (min) t 4 13 100 ns (max) Bus Relinquish Time after Rising Edge of CS 10 ns (min) NOTES 1Sample tested during initial release and after any redesign or process change that may affect this parameter. All input signals are specified with tr = tf = 5 ns (10% to 90%) and timed from a voltage level of 1.6 V. 2See Figures 2 and 3 and Serial Interface section of this data sheet. 3Measured with the load circuit in Figure 1 and defined as the time required for the output to cross 0.8 V or 2.4 V. 4Derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit in Figure 1. The measured number is then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time quoted in the timing characteristics is the true bus relinquish time of the part and is independent of the bus loading.
200 A IOL TO OUTPUT 2.1V PIN CL 50pF 1.6mA IOH
Figure 1. Load Circuit for Timing Specifications
t8 CS t t t 1 2 t3 6 t7 t SCLK 7 t4 t5 DIN 1 0 0 A4 A3 A2 A1 A0 DB7 DB0 DB7 DB0 COMMAND BYTE MOST SIGNIFICANT BYTE LEAST SIGNIFICANT BYTE
Figure 2. Serial Write Timing
CS t1 t t9 t 13 10 SCLK DIN 0 0 0 A4 A3 A2 A1 A0 t t t 12 11 11 DOUT DB7 DB0 DB7 DB0 COMMAND BYTE MOST SIGNIFICANT BYTE LEAST SIGNIFICANT BYTE
Figure 3. Serial Read Timing REV. A –5– Document Outline FEATURES GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS SPECIFICATIONS TIMING CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS ORDERING GUIDE PIN CONFIGURATION PIN FUNCTION DESCRIPTIONS TERMINOLOGY MEASUREMENT ERROR PHASE ERROR BETWEEN CHANNELS POWER SUPPLY REJECTION ADC OFFSET ERROR GAIN ERROR GAIN ERROR MATCH Typical Performance Characteristics Test Circuits ANALOG INPUTS di/dt CURRENT SENSOR AND DIGITAL INTEGRATOR ZERO CROSSING DETECTION LINE VOLTAGE SAG DETECTION Sag Level Set POWER SUPPLY MONITOR INTERRUPTS Using the ADE7759 Interrupts with an MCU Interrupt Timing TEMPERATURE MEASUREMENT ANALOG-TO-DIGITAL CONVERSION Antialias Filter ADC Transfer Function Reference Circuit CHANNEL 1 ADC Channel 1 ADC Gain Adjust Channel 1 Sampling CHANNEL 1 AND CHANNEL 2 WAVEFORM SAMPLING MODE CHANNEL 2 ADC Channel 2 Sampling PHASE COMPENSATION ACTIVE POWER CALCULATION ENERGY CALCULATION Integration Time under Steady Load POWER OFFSET CALIBRATION ENERGY-TO-FREQUENCY CONVERSION LINE CYCLE ENERGY ACCUMULATION MODE CALIBRATING THE ENERGY METER Calculating the Average Active Power Calibrating the Frequency at CF Energy Meter Display CLKIN FREQUENCY SUSPENDING THE ADE7759 FUNCTIONALITY APPLICATION INFORMATION SERIAL INTERFACE Serial Write Operation Serial Read Operation CHECKSUM REGISTER REGISTER DESCRIPTIONS Communications Register Mode Register (06H) Interrupt Status Register (04H) Reset Interrupt Status Register (05H) CH1OS Register (08H) OUTLINE DIMENSIONS Revision History