Datasheet ADE5169, ADE5569 (Analog Devices) - 7

link to page 25
Data Sheet ADE5169/ADE5569 SPECIFICATIONS
VDD = 3.3 V ± 5%, AGND = DGND = 0 V, on-chip reference XTALx = 32.768 kHz, TMIN to TMAX = −40°C to +85°C, unless otherwise noted.
ENERGY METERING Table 2. Parameter Min Typ Max Unit Test Conditions/Comments
MEASUREMENT ACCURACY1 Phase Error Between Channels PF = 0.8 Capacitive ±0.05 Degrees Phase lead: 37° PF = 0.5 Inductive ±0.05 Degrees Phase lag: 60° Active Energy Measurement Error2 0.1 % of reading Over a dynamic range of 1000 to 1 at 25°C AC Power Supply Rejection2 V = 3.3 V + 100 mV rms/120 Hz DD Output Frequency Variation 0.01 % I = V = ±100 mV rms Px P DC Power Supply Rejection2 V = 3.3 V ± 117 mV dc DD Output Frequency Variation 0.01 % Active Energy Measurement Bandwidth1 8 kHz Reactive Energy Measurement Error2 0.5 % of reading Over a dynamic range of 1000 to 1 at 25°C V Measurement Error2 0.5 % of reading Over a dynamic range of 100 to 1 at 25°C rms V Measurement Bandwidth1 63.7 Hz Fundamental only, mean absolute rms measurement I Measurement Error2 0.5 % of reading Over a dynamic range of 500 to 1 at 25°C rms I Measurement Bandwidth1 3.9 kHz rms ANALOG INPUTS Maximum Signal Levels ±500 mV peak V − V differential input P N ADE5169 ±500 mV peak I − I and I − I differential inputs PA N PB N ADE5569 ±500 mV peak I − I P N Input Impedance (DC) 770 kΩ ADC Offset Error2 ±10 mV PGA1 = PGA2 = 1 ±1 mV PGA1 = 16 Gain Error2 Current Channel ±3 % I = I = 0.5 V dc or I = 0.5 V dc PA PB P Voltage Channel ±3 % V − V = 0.5 V dc P N Gain Error Match ±0.2 % CF1 AND CF2 PULSE OUTPUT Maximum Output Frequency 21.6 kHz V − V = 500 mV peak; I − I = 500 mV for P N PA N the ADE5169; I − I = 500 mV for the P N ADE5569 Duty Cycle 50 % If the CF1 or CF2 frequency > 5.55 Hz Active High Pulse Width 90 ms If the CF1 or CF2 frequency < 5.55 Hz FAULT DETECTION3 Fault Detection Threshold Inactive Input ≠ Active Input 6.25 % of active I or I active PA PB Input Swap Threshold Inactive Input > Active Input 6.25 % of active I or I active PA PB Accuracy Fault Mode Operation I Active, I = AGND 0.1 % of reading Over a dynamic range of 500 to 1 PA PB I Active, I = AGND 0.1 % of reading Over a dynamic range of 500 to 1 PB PA Fault Detection Delay 3 Seconds Swap Delay 3 Seconds 1 These specifications are not production tested but are guaranteed by design and/or characterization data on production release. 2 See Terminologysection for definition. 3 Available only in the ADE5169. Rev. E | Page 7 of 155 Document Outline GENERAL FEATURES ENERGY MEASUREMENT FEATURES MICROPROCESSOR FEATURES REVISION HISTORY GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAMS SPECIFICATIONS ENERGY METERING ANALOG PERIPHERALS DIGITAL INTERFACE TIMING SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY SPECIAL FUNCTION REGISTER (SFR) MAPPING POWER MANAGEMENT POWER MANAGEMENT REGISTER DETAILS Writing to the Interrupt Pins Configuration SFR (INTPR, Address 0xFF) Clearing the Scratch Pad Registers (SCRATCH1, Address 0xFB to SCRATCH4, Address 0xFE) Writing to the Power Control SFR (POWCON, Address 0xC5) POWER SUPPLY ARCHITECTURE BATTERY SWITCHOVER Switching from VDD to VBAT Switching from VBAT to VDD POWER SUPPLY MANAGEMENT (PSM) INTERRUPT Battery Switchover and Power Supply Restored PSM Interrupt VDCINADC PSM Interrupt VBAT Monitor PSM Interrupt VDCIN Monitor PSM Interrupt SAG Monitor PSM Interrupt USING THE POWER SUPPLY FEATURES OPERATING MODES PSM0 (NORMAL MODE) PSM1 (BATTERY MODE) PSM2 (SLEEP MODE) 3.3 V PERIPHERALS AND WAKE-UP EVENTS TRANSITIONING BETWEEN OPERATING MODES Automatic Battery Switchover (PSM0 to PSM1) Entering Sleep Mode (PSM1 to PSM2) Servicing Wake-Up Events (PSM2 to PSM1) Automatic Switch to VDD (PSM2 to PSM0) Automatic Switch to VDD (PSM1 to PSM0) USING THE POWER MANAGEMENT FEATURES ENERGY MEASUREMENT ACCESS TO ENERGY MEASUREMENT SFRs ACCESS TO INTERNAL ENERGY MEASUREMENT REGISTERS Writing to the Internal Energy Measurement Registers Reading the Internal Energy Measurement Registers ENERGY MEASUREMENT REGISTERS ENERGY MEASUREMENT INTERNAL REGISTERS DETAILS INTERRUPT STATUS/ENABLE SFRS ANALOG INPUTS ANALOG-TO-DIGITAL CONVERSION Antialiasing Filter ADC Transfer Function Current Channel ADC Voltage Channel ADC Channel Sampling FAULT DETECTION (ADE5169 ONLY) Channel Selection Indication Fault Indication Fault with Active Input Greater Than Inactive Input Fault with Inactive Input Greater Than Active Input Calibration Concerns di/dt CURRENT SENSOR AND DIGITAL INTEGRATOR POWER QUALITY MEASUREMENTS Zero-Crossing Detection Zero-Crossing Timeout Period or Frequency Measurements Line Voltage SAG Detection SAG Level Set Peak Detection Peak Level Set Peak Level Record PHASE COMPENSATION RMS CALCULATION Current Channel RMS Calculation Current Channel RMS Offset Compensation Voltage Channel RMS Calculation Voltage Channel RMS Offset Compensation ACTIVE POWER CALCULATION Active Power Gain Calibration Active Power Offset Calibration Active Power Sign Detection Active Power No Load Detection ACTIVE ENERGY CALCULATION Integration Time Under Steady Load—Active Energy Active Energy Accumulation Modes Watt Signed Accumulation Mode Watt Positive Only Accumulation Mode Watt Absolute Accumulation Mode Active Energy Pulse Output Line Cycle Active Energy Accumulation Mode REACTIVE POWER CALCULATION Reactive Power Gain Calibration Reactive Power Offset Calibration Sign of Reactive Power Calculation Reactive Power Sign Detection Reactive Power No Load Detection REACTIVE ENERGY CALCULATION Integration Time Under Steady Load—Reactive Energy Reactive Energy Accumulation Modes Var Signed Accumulation Mode Var Antitamper Accumulation Mode Var Absolute Accumulation Mode Reactive Energy Pulse Output Line Cycle Reactive Energy Accumulation Mode APPARENT POWER CALCULATION Apparent Power Offset Calibration APPARENT ENERGY CALCULATION Integration Times Under Steady Load—Apparent Energy Apparent Energy Pulse Output Line Cycle Apparent Energy Accumulation Mode Apparent Power No Load Detection AMPERE-HOUR ACCUMULATION ENERGY TO FREQUENCY CONVERSION Pulse Output Configuration Pulse Output Characteristic ENERGY REGISTER SCALING ENERGY MEASUREMENT INTERRUPTS TEMPERATURE, BATTERY, AND SUPPLY VOLTAGE MEASUREMENTS TEMPERATURE MEASUREMENT Single Temperature Measurement Background Temperature Measurements Temperature ADC in PSM0, PSM1, and PSM2 Modes Temperature ADC Interrupt BATTERY MEASUREMENT Single Battery Measurement Background Battery Measurements Battery ADC in PSM0, PSM1, and PSM2 Modes Battery ADC Interrupt EXTERNAL VOLTAGE MEASUREMENT Single External Voltage Measurement Background External Voltage Measurements External Voltage ADC in PSM1 and PSM2 Modes External Voltage ADC Interrupt 8052 MCU CORE ARCHITECTURE MCU REGISTERS BASIC 8052 REGISTERS Program Counter (PC) Instruction Register (IR) Register Banks Accumulator B Register Program Status Word (PSW) Data Pointer (DPTR) Stack Pointer (SP) Stack Boundary Protection STANDARD 8052 SFRS Timer SFRs Serial Port SFRs Interrupt SFR I/O Port SFRs Power Control Register (PCON, Address 0x87) MEMORY OVERVIEW General-Purpose RAM Special Function Registers (SFRs) Extended Internal RAM (XRAM) Code Memory ADDRESSING MODES Immediate Addressing Direct Addressing Indirect Addressing Extended Direct Addressing Extended Indirect Addressing Code Indirect Addressing INSTRUCTION SET READ-MODIFY-WRITE INSTRUCTIONS INSTRUCTIONS THAT AFFECT FLAGS ADD A, Source ADDC A, Source SUBB A, Source MUL AB DIV AB DA A RRC A RLC A CJNE Destination, Source, Relative Jump DUAL DATA POINTERS INTERRUPT SYSTEM STANDARD 8052 INTERRUPT ARCHITECTURE INTERRUPT ARCHITECTURE INTERRUPT REGISTERS INTERRUPT PRIORITY INTERRUPT FLAGS INTERRUPT VECTORS INTERRUPT LATENCY CONTEXT SAVING WATCHDOG TIMER WRITING TO THE WATCHDOG TIMER SFR (WDCON, ADDRESS 0xC0) WATCHDOG TIMER INTERRUPT LCD DRIVER LCD REGISTERS LCD SETUP LCD TIMING AND WAVEFORMS Software Controlled Blink Mode Automatic Blink Mode SCROLLING MODE Automatic Scrolling Mode DISPLAY ELEMENT CONTROL Writing to LCD Data Registers Reading LCD Data Registers VOLTAGE GENERATION Lifetime Performance Power Consumption Contrast Control Lifetime Performance LCD EXTERNAL CIRCUITRY Charge Pump External Resistor Ladder LCD FUNCTION IN PSM2 MODE Example LCD Setup FLASH MEMORY FLASH MEMORY OVERVIEW Flash/EE Memory Reliability FLASH MEMORY ORGANIZATION USING THE FLASH MEMORY ECON—Flash Control SFR Flash Functions Write Byte Erase Page Erase All Read Byte PROTECTING THE FLASH MEMORY Enabling Flash Protection by Code Enabling Flash Protection by Emulator Commands Notes on Flash Protection Flash Memory Timing IN-CIRCUIT PROGRAMMING Serial Downloading TIMERS TIMER REGISTERS TIMER 0 AND TIMER 1 Timer 0 High/Low and Timer 1 High/Low Data Registers Timer/Counter 0 and Timer/Counter 1 Operating Modes Mode 0 (13-Bit Timer/Counter) Mode 1 (16-Bit Timer/Counter) Mode 2 (8-Bit Timer/Counter with Autoreload) Mode 3 (Two 8-Bit Timer/Counters) TIMER 2 Timer/Counter 2 Data Registers Timer/Counter 2 Operating Modes 16-Bit Autoreload Mode 16-Bit Capture Mode PHASE-LOCKED LOOP (PLL) PLL REGISTERS Writing to the Power Control SFR (POWCON, Address 0xC5) REAL-TIME CLOCK (RTC) ACCESS TO RTC SFRs ACCESS TO INTERNAL RTC REGISTERS Writing to Internal RTC Registers Reading Internal RTC Registers RTC SFRS RTC REGISTERS RTC CALENDAR RTC INTERRUPTS Interval Timer Alarm RTC Wake-Up Alarm RTC CRYSTAL COMPENSATION RTC Calibration Calibration Flow UART SERIAL INTERFACE UART SFRs UART OPERATION MODES Mode 0 (Shift Register with Baud Rate Fixed at fCORE/12) Mode 1 (8-Bit UART with Variable Baud Rate) Mode 2 (9-Bit UART with Baud Rate Fixed at fCORE/64 or fCORE/32) Mode 3 (9-Bit UART with Variable Baud Rate) UART BAUD RATE GENERATION Mode 0 Baud Rate Generation Mode 2 Baud Rate Generation Mode 1 and Mode 3 Baud Rate Generation Timer 1 Generated Baud Rates Timer 2 Generated Baud Rates UART Timer Generated Baud Rates UART ADDITIONAL FEATURES Enhanced Error Checking UART TxD Signal Modulation UART2 SERIAL INTERFACE UART2 SFRS UART2 OPERATION MODES 9-Bit UART2 with Variable Baud Rate UART2 BAUD RATE GENERATION UART2 Timer Generated Baud Rates UART2 ADDITIONAL FEATURES Enhanced Error Checking SERIAL PERIPHERAL INTERFACE (SPI) SPI REGISTERS SPI PINS MISO (Master In, Slave Out Data I/O Pin) MOSI (Master Out, Slave In Pin) SCLK (Serial Clock I/O Pin) /SS (Slave Select Pin) SPI MASTER OPERATING MODES Procedures for Using SPI as a Master SingleByte Write Mode, SPICONT (SPIMOD2[7]) = 0 Continuous Mode, SPICONT (SPIMOD2[7]) = 1 SPI INTERRUPT AND STATUS FLAGS I2C-COMPATIBLE INTERFACE SERIAL CLOCK GENERATION SLAVE ADDRESSES I2C REGISTERS READ AND WRITE OPERATIONS Reading the SPI/I2C Receive Buffer SFR (SPI2CRx, Address 0x9B) I2C RECEIVE AND TRANSMIT FIFOS I/O PORTS PARALLEL I/O Weak Internal Pull-Ups Enabled Open Drain (Weak Internal Pull-Ups Disabled) 38 kHz Modulation I/O REGISTERS PORT 0 PORT 1 PORT 2 DETERMINING THE VERSION OF THE ADE5169/ADE5569 OUTLINE DIMENSIONS ORDERING GUIDE