Datasheet LTC1759 (Analog Devices) - 7

LTC1759
U U U PIN FUNCTIONS Input Power-Related Pins SW (Pin 3):
This pin is the reference point for the floating topside gate drive circuitry. It is the common connection
UV (Pin 7):
Charger Section Undervoltage Lockout Pin. for the top and bottom side switches and the output The rising threshold is 6.7V with a hysteresis of 0.5V. inductor. This pin switches between ground and V Switching stops in undervoltage lockout. Connect this CC with very high dv/dt rates. Care needs to be taken in the PC input to the input voltage source with no resistor divider. layout to keep this node from coupling to other sensitive UV must be pulled below 0.7V when there is no input nodes. A 1A Schottky clamping diode should be placed voltage source (5k resistor from adapter output to ground very close to the chip from the ground pin to this pin to is required) to obtain the lowest quiescent battery current. prevent the chip substrate diode from turning on. See
INFET (Pin 8):
Gate Drive to Input P-channel FET. For very Applications Information for more details. low dropout applications, use an external P-channel FET to
SYNC (Pin 4):
External Clock Synchronization Input. Pulse connect the adapter output and VCC. INFET is clamped to width range: 10% to 90%. 7.8V below VCC.
SDB (Shutdown Bar) (Pin 5):
Active Low Digital Input. The
CLP (Pin 9):
Positive Input to the Input Current Limit charger is disabled when asserted. This pin is connected Amplifier CL1. When used to limit supply current, a filter to the CHGEN pin to enable charger control through the (R3 and C1 of Figure 10) is needed to filter out the SMBus interface. switching noise. The threshold is set at 92mV.
CHGEN (Pin 12):
Digital Output to Enable Charger Func-
CLN (Pin 10):
Negative Input to the Input Current Limit tion. Connect CHGEN to SDB. Amplifier CL1. It should be connected to VCC (to the VCC bypass capacitor C2 for less noise).
ISET (Pin 17):
Open-Drain CMOS Switch to DGND. An external resistor, R
COMP1 (Pin 11):
Compensation Node for the Input Cur- SET, is connected from ISET to the current programming input, the PROG pin of the battery rent Limit Amplifier CL1. At input adapter current limit, this charger section, which sets the range of the charging node rises to 1V. By forcing COMP1 low with an external current. transistor, amplifier CL1 will be defeated (no adapter current limit). COMP1 can source 200µA. Ground (to
ILIMIT (Pin 24):
An external resistor is connected between AGND) this pin if the adapter current limiting function is this pin and DGND. The value of the external resistor not used. programs the range and resolution of the programmed charger current. See Electrical Characteristics table for
Battery Charging-Related Pins
more information.
BOOST (Pin 1):
This pin is used to bootstrap and supply
VLIMIT (Pin 25):
An external resistor is connected between power for the topside power switch gate drive and control this pin and DGND. The value of the external resistor circuity. In normal operation, VBOOST is powered from an programs the range and resolution of the VSET divider. See internally generated 8.6V regulator VGBIAS, VBOOST ≈ VCC Electrical Characteristics table for more information. + 9.1V when TGATE is high. Do not force an external voltage on BOOST pin.
VSET (Pin 26):
This is the tap point of the programmable resistor divider, which provides battery voltage feedback
TGATE (Pin 2):
This pin provides gate drive to the topside to the charger. power FET. When TGATE is driven on, the gate voltage will be approximately equal to VSW + 6.6V. A series resistor of 5Ω to 10Ω should be used from this pin to the gate of the topside FET. 7