Datasheet LTC4007-1 (Analog Devices) - 9

LTC4007-1
TesT circuiT
LTC4007-1 CHEM 13 VREF + DIVIDER/ EA MUX 3C4C 5 – CSP BAT ITH 11 12 8 + LT1055 – 0.6V 40071 TC
operaTion Overview
to 10% of the full-scale charge current, an internal C/10 The LTC4007-1 is a synchronous current mode PWM comparator will indicate this condition by latching the step-down (buck) switcher battery charger controller. The FLAG pin low. The charge timer is also reset to 1/4 of the charge current is programmed by the combination of a total charge time when FLAG goes low. If this condition program resistor (R is caused by an input current limit condition, described PROG) from the PROG pin to ground and a sense resistor (R below, then the FLAG indicator will be inhibited. When a SENSE) between the CSP and BAT pins. The final float voltage is programmed to one of four time-out occurs, charging is terminated immediately and values (12.3V, 12.6V, 16.4V, 16.8V) with ±1% maximum the CHG pin is forced to a high impedance state. To restart accuracy using pins 3C4C and CHEM. Charging begins the charge cycle manually, simply remove the input volt- when the potential at the DCIN pin rises above the volt- age and reapply it, or set the SHDN pin high momentarily. age at BAT (and the UVLO voltage) and the SHDN pin When the input voltage is not present, the charger goes is low; the CHG pin is set low. At the beginning of the into a sleep mode, dropping battery current drain to 15µA. charge cycle, if the cell voltage is below 3.25V (3.173V This greatly reduces the current drain on the battery and if CHEM is low), the LOBAT pin will be low. The LOBAT increases the standby time. The charger is inhibited any indicator can be used to reduce the charging current to time the SHDN pin is high. a low value, typically 10% of full scale. If the cell voltage
Input FET
stays below 3.25V for 25% of the total charge time, the charge sequence will be terminated immediately and the The input FET circuit performs two functions. It enables FAULT pin will be set low. the charger if the input voltage is higher than the CLN pin and provides the logic indicator of AC present on the ACP An external thermistor network is sampled at regular pin. It controls the gate of the input FET to keep a low intervals. If the thermistor value exceeds design limits, forward voltage drop when charging and also prevents charging is suspended and the FAULT pin is set low. If the reverse current flow through the input FET. thermistor value returns to an acceptable value, charging resumes and the FAULT pin is set high. An external resistor If the input voltage is less than VCLN, it must go at least on the RT pin sets the total charge time. The timer can be 170mV higher than VCLN to activate the charger. When defeated by forcing the CHG pin to a low voltage. this occurs the ACP pin is released and pulled up with an external load to indicate that the adapter is present. As the battery approaches the final float voltage, the charge current will begin to decrease. When the current drops 40071fa For more information www.linear.com/LTC4007-1 9 Document Outline Description Typical Application Absolute Maximum Ratings Typical Performance Characteristics Pin Functions Block Diagram Operation Typical Application Related Parts