Datasheet LT3761, LT3761-1 (Analog Devices) - 9

HerstellerAnalog Devices
Beschreibung60VIN LED Controller with Internal PWM Generator
Seiten / Seite32 / 9 — pin FuncTions. RT (Pin 11):. EN/UVLO (Pin 12):. SYNC (Pin 9, LT3761-1 …
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DokumentenspracheEnglisch

pin FuncTions. RT (Pin 11):. EN/UVLO (Pin 12):. SYNC (Pin 9, LT3761-1 Only):. INTVCC (Pin 13):. DIM/SS (Pin 10):. VIN (Pin 14):

pin FuncTions RT (Pin 11): EN/UVLO (Pin 12): SYNC (Pin 9, LT3761-1 Only): INTVCC (Pin 13): DIM/SS (Pin 10): VIN (Pin 14):

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LT3761/LT3761-1
pin FuncTions
difference between current sense inputs ISP and ISN is
RT (Pin 11):
Switching Frequency Adjustment Pin. Set the less than 25mV. To function, the pin requires an external frequency using a resistor to GND (for resistor values, see pull-up resistor, usually to INTVCC. When the PWM input the Typical Performance curve or Table 2). Do not leave is low and the DC/DC converter is idle, the OPENLED the RT pin open. Place the resistor close to the IC. condition is latched to the last valid state when the PWM
EN/UVLO (Pin 12):
Enable and Undervoltage Detect Pin. input was high. When PWM input goes high again, the An accurate 1.22V falling threshold with externally pro- OPENLED pin will be updated. This pin may be used to grammable hysteresis causes the switching regulator to report transition from constant current regulation to con- shut down when power is insufficient to maintain output stant voltage regulation modes, for instance in a charger regulation. Above the 1.24V (typical) rising enable threshold or current limited voltage supply. (but below 2.5V), EN/UVLO input bias current is sub-μA.
SYNC (Pin 9, LT3761-1 Only):
The SYNC pin is used to Below the 1.22V (typical) falling threshold, an accurate synchronize the internal oscillator to an external logic level 2.3μA (typical) pull-down current is enabled so the user signal. The RT resistor should be chosen to program an can define the rising hysteresis with the external resistor internal switching frequency 20% slower than the SYNC selection. An undervoltage condition causes the GATE pulse frequency. Gate turn-on occurs a fixed delay after and PWMOUT pins to transition low and resets soft-start. the rising edge of SYNC. For best PWM performance, the Tie to 0.4V, or less, to disable the device and reduce VIN PWM rising edge should occur at least 200ns before the quiescent current below 1μA. SYNC rising edge. Use a 50% duty cycle waveform to drive this pin. This pin replaces OPENLED on LT3761-1 option
INTVCC (Pin 13):
Current limited, low dropout linear regula- parts. If not used, tie this pin to PWMOUT. tor regulates to 7.85V (typical) from VIN. Supplies internal loads, GATE and PWMOUT drivers. Must be bypassed with
DIM/SS (Pin 10):
Soft-Start and PWMOUT Dimming Signal a 1µF ceramic capacitor placed close to the pin and to the Generator Programming Pin. This pin modulates switching exposed pad GND of the IC. regulator frequency and compensation pin voltage (VC) clamp when it is below 1V. The soft-start interval is set
VIN (Pin 14):
Power Supply for Internal Loads and INTVCC with an external capacitor and the DIM/SS pin charging Regulator. Must be locally bypassed with a 0.22µF (or current. The pin has an internal 12μA (typical) pull-up larger) low ESR capacitor placed close to the pin. current source. The soft-start pin is reset to GND by an
SENSE (Pin 15):
The Current Sense Input for the Switch undervoltage condition (detected at the EN/UVLO pin), Control Loop. Kelvin connect the SENSE pin to the positive INTVCC undervoltage, overcurrent event sensed at ISP/ terminal of the switch current sense resistor in the source ISN, or thermal limit. After initial start-up with EN/UVLO, of the external power NFET. The negative terminal of the DIM/SS is forced low until the first PWM rising edge. When switch current sense resistor should be Kelvin connected DIM/SS reaches the steady-state voltage (~1.17V), the to the exposed pad (GND) of the LT3761/LT3761-1. charging current (sum of internal and external currents) is sensed and used to set the PWM pin charging and discharge
GATE (Pin 16):
N-channel FET Gate Driver Output. Switches currents and threshold hysteresis. In this manner, the SS between INTVCC and GND. Driven to GND during shutdown, charging current sets the duty cycle of the PWMOUT signal fault or idle states. generator associated with the PWM pin. This pin should
GND (Exposed Pad Pin 17):
Ground. This pin also serves always have a capacitor to GND, minimum 560pF value, as current sense input for the control loop, sensing the when used with the PWMOUT signal generator function. negative terminal of the current sense resistor. Solder the Place the PWM pin capacitor close to the IC. exposed pad directly to the ground plane. 37611fb For more information www.linear.com/LT3761 9 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Typical Performance Characteristics Pin Functions Block Diagram Operation Applications Information Typical Applications Package Description Revision History Typical Application Related Parts