Datasheet ADP5091, ADP5092 (Analog Devices) - 8
| Hersteller | Analog Devices |
| Beschreibung | Ultralow Power Energy Harvester PMU with MPPT and Charge Management |
| Seiten / Seite | 28 / 8 — ADP5091/ADP5092. Data Sheet. PIN CONFIGURATIONS AND FUNCTION … |
| Revision | A |
| Dateiformat / Größe | PDF / 931 Kb |
| Dokumentensprache | Englisch |
ADP5091/ADP5092. Data Sheet. PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS. _D0. _D1. GOOD. REF 1. 18 BACK_UP. SETSD 2. 17 BAT. SETBK 3
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ADP5091/ADP5092 Data Sheet PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS W P W _D0 _D1 P _D0 _D1 _S G G _S S NO G G I D S NO GOOD I D GOOD RE RE DI M VI P RE RE DI M VI P 24 23 22 21 20 19 24 23 22 21 20 19 REF 1 18 BACK_UP REF 1 18 BACK_UP SETSD 2 17 BAT SETSD 2 17 BAT SETBK 3 ADP5091 16 SYS SETBK 3 ADP5092 16 SYS TERM TOP VIEW 4 TOP VIEW 15 REG_FB TERM 4 15 REG_FB (Not to Scale) (Not to Scale) SETPG 5 14 REG_OUT SETPG 5 14 REG_OUT SETHYST 6 13 SW SETHYST 6 13 SW 7 8 9 1 7 8 9 1 10 1 12 10 1 12 P N P N ND ND ND VI ND CB VI LLD G CB G AG MPPT P AG MPPT GOOD P G_
002
NOTES E R 1. THE EXPOSED PAD MUST BE CONNECTED TO AGND.
14145- 003
NOTES 1. THE EXPOSED PAD MUST BE CONNECTED TO AGND.
14145- Figure 3. ADP5091 Pin Configuration Figure 4. ADP5092 Pin Configuration
Table 5. Pin Function Descriptions Pin No.1 ADP5091 ADP5092 Mnemonic Description
1 1 REF Internal Voltage Reference Monitoring Node for the SETSD, SETPG, SETBK, and TERM Pins. 2 2 SETSD Shutdown Setting. The SETSD pin sets the shutdown discharging voltage based on the BAT pin voltage level. 3 3 SETBK BACK_UP Disabled Threshold Monitoring BAT Voltage Setting. Connect the SETBK pin to the AGND pin without the BACK_UP storage element. 4 4 TERM Termination Charging Voltage. This pin sets the termination charging voltage based on the BAT pin voltage level. 5 5 SETPG Power-Good Rising Threshold Monitoring SYS Node Voltage Level Setting. 6 6 SETHYST PGOOD Falling Hysteresis Setting. Connect a resistor between SETPG and SETHYST to program the PGOOD falling hysteresis. 7 7 AGND Analog Ground. 8 8 CBP Capacitor Bypass. This pin samples and holds the maximum power point level. Connect a 10 nF capacitor from the CBP pin to the AGND pin. When the MPPT pin is disabled, tie the CBP pin to an external reference that is lower than the VIN pin. 9 9 MPPT Maximum Power Point Tracking. This pin sets the maximum power point ratio for the different energy harvesters with a resistor divider. In no sensing mode, place a resistor through AGND to set the MPPT voltage. The typical current value is 2.0 µA. 10 10 VIN Input Supply from Energy Harvester Source. Connect at least a 10 µF capacitor as close as possible between VIN and PGND. 11 N/A LLD Low Light Density Indicator to Microcontroller for the ADP5091. LLD pul s high at the MINOP voltage higher than the CBP voltage. N/A 11 REG_GOOD Regulated Output Power Good for the ADP5092. 12 12 PGND Power Ground. 13 13 SW Switching Node for the Inductive Boost Regulator with a Connection to an External Inductor. Connect a 22 µH inductor between SW and VIN. 14 14 REG_OUT Regulated Output. Connect at least a 4.7 µF capacitor as close as possible between REG_OUT and PGND. 15 15 REG_FB Regulated Output Feedback Voltage Sense Input. The fixed output connects this pin to REG_OUT. The adjustable output connects this pin to a resistor divider from REG_OUT. 16 16 SYS Output Supply to System Load. Connect at least a 4.7 µF capacitor as close as possible between SYS and PGND. 17 17 BAT SYS Output Supply Storage. This pin places the rechargeable battery or super capacitor as a storage for the SYS output supply. 18 18 BACK_UP Optional Input Supply from the Backup Primary Battery Cell. Rev. A | Page 8 of 28 Document Outline FEATURES APPLICATIONS TYPICAL APPLICATION CIRCUIT GENERAL DESCRIPTION REVISION HISTORY DETAILED FUNCTIONAL BLOCK DIAGRAM SPECIFICATIONS REGULATED OUTPUT SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION FAST COLD START-UP CIRCUIT (VSYS < VSYS_TH, VIN > VIN_COLD) MAIN BOOST REGULATOR (VBAT_TERM > VSYS > VSYS_TH) VIN OPEN CIRCUIT AND MPPT MINIMUM OPERATION THRESHOLD FUNCTION DISABLING BOOST REGULATED OUTPUT WORKING MODE REG_D0 AND REG_D1 REGULATED OUTPUT CONFIGURATION REG_GOOD (ADP5092 ONLY) ENERGY STORAGE CHARGE MANAGEMENT BACKUP STORAGE PATH BACKUP AND BAT SELECTION THRESHOLD BATTERY OVERCHARGING PROTECTION BATTERY DISCHARGING PROTECTION POWER GOOD (PGOOD) POWER PATH WORKING FLOW CURRENT-LIMIT AND SHORT-CIRCUIT PROTECTION THERMAL SHUTDOWN APPLICATIONS INFORMATION ENERGY HARVESTER SELECTION ENERGY STORAGE ELEMENT SELECTION INDUCTOR SELECTION CAPACITOR SELECTION Input Capacitor SYS Capacitor REG_OUT Capacitor CBP Capacitor LAYOUT AND ASSEMBLY CONSIDERATIONS TYPICAL APPLICATION CIRCUITS FACTORY PROGRAMMABLE OPTIONS OUTLINE DIMENSIONS ORDERING GUIDE
ADP5091/ADP5092 Data Sheet PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS W P W _D0 _D1 P _D0 _D1 _S G G _S S NO G G I D S NO GOOD I D GOOD RE RE DI M VI P RE RE DI M VI P 24 23 22 21 20 19 24 23 22 21 20 19 REF 1 18 BACK_UP REF 1 18 BACK_UP SETSD 2 17 BAT SETSD 2 17 BAT SETBK 3 ADP5091 16 SYS SETBK 3 ADP5092 16 SYS TERM TOP VIEW 4 TOP VIEW 15 REG_FB TERM 4 15 REG_FB (Not to Scale) (Not to Scale) SETPG 5 14 REG_OUT SETPG 5 14 REG_OUT SETHYST 6 13 SW SETHYST 6 13 SW 7 8 9 1 7 8 9 1 10 1 12 10 1 12 P N P N ND ND ND VI ND CB VI LLD G CB G AG MPPT P AG MPPT GOOD P G_
002
NOTES E R 1. THE EXPOSED PAD MUST BE CONNECTED TO AGND.
14145- 003
NOTES 1. THE EXPOSED PAD MUST BE CONNECTED TO AGND.
14145- Figure 3. ADP5091 Pin Configuration Figure 4. ADP5092 Pin Configuration
Table 5. Pin Function Descriptions Pin No.1 ADP5091 ADP5092 Mnemonic Description
1 1 REF Internal Voltage Reference Monitoring Node for the SETSD, SETPG, SETBK, and TERM Pins. 2 2 SETSD Shutdown Setting. The SETSD pin sets the shutdown discharging voltage based on the BAT pin voltage level. 3 3 SETBK BACK_UP Disabled Threshold Monitoring BAT Voltage Setting. Connect the SETBK pin to the AGND pin without the BACK_UP storage element. 4 4 TERM Termination Charging Voltage. This pin sets the termination charging voltage based on the BAT pin voltage level. 5 5 SETPG Power-Good Rising Threshold Monitoring SYS Node Voltage Level Setting. 6 6 SETHYST PGOOD Falling Hysteresis Setting. Connect a resistor between SETPG and SETHYST to program the PGOOD falling hysteresis. 7 7 AGND Analog Ground. 8 8 CBP Capacitor Bypass. This pin samples and holds the maximum power point level. Connect a 10 nF capacitor from the CBP pin to the AGND pin. When the MPPT pin is disabled, tie the CBP pin to an external reference that is lower than the VIN pin. 9 9 MPPT Maximum Power Point Tracking. This pin sets the maximum power point ratio for the different energy harvesters with a resistor divider. In no sensing mode, place a resistor through AGND to set the MPPT voltage. The typical current value is 2.0 µA. 10 10 VIN Input Supply from Energy Harvester Source. Connect at least a 10 µF capacitor as close as possible between VIN and PGND. 11 N/A LLD Low Light Density Indicator to Microcontroller for the ADP5091. LLD pul s high at the MINOP voltage higher than the CBP voltage. N/A 11 REG_GOOD Regulated Output Power Good for the ADP5092. 12 12 PGND Power Ground. 13 13 SW Switching Node for the Inductive Boost Regulator with a Connection to an External Inductor. Connect a 22 µH inductor between SW and VIN. 14 14 REG_OUT Regulated Output. Connect at least a 4.7 µF capacitor as close as possible between REG_OUT and PGND. 15 15 REG_FB Regulated Output Feedback Voltage Sense Input. The fixed output connects this pin to REG_OUT. The adjustable output connects this pin to a resistor divider from REG_OUT. 16 16 SYS Output Supply to System Load. Connect at least a 4.7 µF capacitor as close as possible between SYS and PGND. 17 17 BAT SYS Output Supply Storage. This pin places the rechargeable battery or super capacitor as a storage for the SYS output supply. 18 18 BACK_UP Optional Input Supply from the Backup Primary Battery Cell. Rev. A | Page 8 of 28 Document Outline FEATURES APPLICATIONS TYPICAL APPLICATION CIRCUIT GENERAL DESCRIPTION REVISION HISTORY DETAILED FUNCTIONAL BLOCK DIAGRAM SPECIFICATIONS REGULATED OUTPUT SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION FAST COLD START-UP CIRCUIT (VSYS < VSYS_TH, VIN > VIN_COLD) MAIN BOOST REGULATOR (VBAT_TERM > VSYS > VSYS_TH) VIN OPEN CIRCUIT AND MPPT MINIMUM OPERATION THRESHOLD FUNCTION DISABLING BOOST REGULATED OUTPUT WORKING MODE REG_D0 AND REG_D1 REGULATED OUTPUT CONFIGURATION REG_GOOD (ADP5092 ONLY) ENERGY STORAGE CHARGE MANAGEMENT BACKUP STORAGE PATH BACKUP AND BAT SELECTION THRESHOLD BATTERY OVERCHARGING PROTECTION BATTERY DISCHARGING PROTECTION POWER GOOD (PGOOD) POWER PATH WORKING FLOW CURRENT-LIMIT AND SHORT-CIRCUIT PROTECTION THERMAL SHUTDOWN APPLICATIONS INFORMATION ENERGY HARVESTER SELECTION ENERGY STORAGE ELEMENT SELECTION INDUCTOR SELECTION CAPACITOR SELECTION Input Capacitor SYS Capacitor REG_OUT Capacitor CBP Capacitor LAYOUT AND ASSEMBLY CONSIDERATIONS TYPICAL APPLICATION CIRCUITS FACTORY PROGRAMMABLE OPTIONS OUTLINE DIMENSIONS ORDERING GUIDE