Datasheet LTC4366 (Analog Devices) - 10
| Hersteller | Analog Devices |
| Beschreibung | High Voltage Surge Stopper |
| Seiten / Seite | 24 / 10 — OPERATION |
| Dateiformat / Größe | PDF / 298 Kb |
| Dokumentensprache | Englisch |
OPERATION
Modelllinie für dieses Datenblatt
- LTC4366CDDB-1#PBF LTC4366CDDB-1#TRMPBF LTC4366CDDB-1#TRPBF LTC4366CDDB-2#PBF LTC4366CDDB-2#TRMPBF LTC4366CDDB-2#TRPBF LTC4366CTS8-1#PBF LTC4366CTS8-1#TRMPBF LTC4366CTS8-1#TRPBF LTC4366CTS8-2#PBF LTC4366CTS8-2#TRMPBF LTC4366CTS8-2#TRPBF LTC4366HDDB-1#PBF LTC4366HDDB-1#TRMPBF LTC4366HDDB-1#TRPBF LTC4366HDDB-2#PBF LTC4366HDDB-2#TRMPBF LTC4366HDDB-2#TRPBF LTC4366HTS8-1#PBF LTC4366HTS8-1#TRMPBF LTC4366HTS8-1#TRPBF LTC4366HTS8-2#PBF LTC4366HTS8-2#TRMPBF LTC4366HTS8-2#TRPBF LTC4366IDDB-1#PBF LTC4366IDDB-1#TRMPBF LTC4366IDDB-1#TRPBF LTC4366IDDB-2#PBF LTC4366IDDB-2#TRMPBF LTC4366IDDB-2#TRPBF LTC4366ITS8-1#PBF LTC4366ITS8-1#TRMPBF LTC4366ITS8-1#TRPBF LTC4366ITS8-2#PBF LTC4366ITS8-2#TRMPBF LTC4366ITS8-2#TRPBF LTC4366MPDDB-1#PBF LTC4366MPDDB-1#TRMPBF LTC4366MPDDB-1#TRPBF LTC4366MPDDB-2#PBF LTC4366MPDDB-2#TRMPBF LTC4366MPDDB-2#TRPBF LTC4366MPTS8-1#PBF LTC4366MPTS8-1#TRMPBF LTC4366MPTS8-1#TRPBF LTC4366MPTS8-2#PBF LTC4366MPTS8-2#TRM LTC4366MPTS8-2#TRMPBF LTC4366MPTS8-2#TRPBF
Textversion des Dokuments
LTC4366
OPERATION
The Simplified Diagram shows three states of operation: Once the OUT to VSS voltage exceeds the 2.55V UVLO1 the start, run and regulate mode. Previous surge stopper threshold, the overvoltage amplifier is enabled. Next, the parts are powered off the input supply, therefore the surge UVLO2 threshold of 4.75V is crossed and the charge pump voltage is limited to the breakdown voltage of the input pins turns on. The charge pump charges the GATE pin with of the part. As demonstrated in run and regulate modes, 20µA to its final value 12V above OUT (clamped by Z4). the majority of this part is powered off the output, so the This allows the capacitor between OUT and VSS to charge MOSFET isolates the surge from the power pins of the until clamped by Z3 to 5.7V. In this run mode the MOSFET part. This allows surge voltages up to the breakdown of is configured as a low resistance pass transistor with little the external MOSFET. voltage drop and power dissipation in the MOSFET. In the start mode a 15µA trickle current flows through RIN, The powered up LTC4366 is now ready to protect the load half is used to charge the gate with the other half used as against an overvoltage transient. The overvoltage regula- bias current. As the GATE pin charges, the external MOSFET tion amplifier monitors the load voltage between OUT and brings up the OUT pin. This leads to the run mode where ground by sensing the voltage on the FB pin with respect the output is high enough to become a supply voltage for to the OUT pin (drop across RFB1). In an overvoltage the charge pump. The charge pump is then used to fully condition the OUT rises until the amplifier drives the M1 charge the gate 12V above the source. gate to regulate and limit the output voltage. This is the With the output voltage equal to the input voltage, it is regulate mode. necessary to protect the load from an input supply over- During regulation the excess voltage is dropped across the voltage. In the regulate mode, the overvoltage regulation MOSFET. To prevent overheating the MOSFET, the LTC4366 amplifier is referenced to the output through a 1.23V limits the overvoltage regulation time using the TIMER pin. reference. If the voltage drop across the upper feedback The TIMER pin is charged with 9µA until the pin exceeds resistor, RFB1, exceeds 1.23V the regulation amplifier pulls 2.8V. At that point an overvoltage fault is set, the MOSFET the gate down to regulate the RFB1 voltage back to 1.23V. is turned off, and the part enters a cool-down period of Therefore, the output voltage is clamped by setting the 9 seconds. The logic and timer block are active during proper ratio between RFB1 and RFB2. cool down while the GATE pin is pulled to OUT. For example, if the output voltage is regulated at 100V then The latched-off version, LTC4366-1, will remain in fault the voltage drop across the RFB2 is 98.77V. If the Zener Z3 until the SD pin is toggled low and then high. Once the fault is 5.7V then the voltage drop across RSS is 94.3V. There- is cleared, the GATE is permitted to turn the MOSFET on fore, when the output is at a high voltage, the majority of again. The auto-retry version, LTC4366-2, waits 9 seconds the voltage is dropped across the two resistors RFB2 and then clears the fault and restarts. RSS. This demonstrates how the LTC4366 floats up with the supply. The adjustable 3-terminal regulators, such as the LT®1085 and LM117, are also based on this idea. The Functional Diagram shows the actual circuits. An external RIN resistor on the VDD pin powers up the 12V shunt regulator which then powers up logic supply, VCC. After verifying that the shutdown input is not active, the GATE pin is charged with a 7.5µA current from VDD. This is the start mode. 436612fe 10 For more information www.linear.com/LTC4366 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Pin Functions Simplified Diagram Functional Diagram Operation Applications Information Package Description Typical Application Related Parts
OPERATION
The Simplified Diagram shows three states of operation: Once the OUT to VSS voltage exceeds the 2.55V UVLO1 the start, run and regulate mode. Previous surge stopper threshold, the overvoltage amplifier is enabled. Next, the parts are powered off the input supply, therefore the surge UVLO2 threshold of 4.75V is crossed and the charge pump voltage is limited to the breakdown voltage of the input pins turns on. The charge pump charges the GATE pin with of the part. As demonstrated in run and regulate modes, 20µA to its final value 12V above OUT (clamped by Z4). the majority of this part is powered off the output, so the This allows the capacitor between OUT and VSS to charge MOSFET isolates the surge from the power pins of the until clamped by Z3 to 5.7V. In this run mode the MOSFET part. This allows surge voltages up to the breakdown of is configured as a low resistance pass transistor with little the external MOSFET. voltage drop and power dissipation in the MOSFET. In the start mode a 15µA trickle current flows through RIN, The powered up LTC4366 is now ready to protect the load half is used to charge the gate with the other half used as against an overvoltage transient. The overvoltage regula- bias current. As the GATE pin charges, the external MOSFET tion amplifier monitors the load voltage between OUT and brings up the OUT pin. This leads to the run mode where ground by sensing the voltage on the FB pin with respect the output is high enough to become a supply voltage for to the OUT pin (drop across RFB1). In an overvoltage the charge pump. The charge pump is then used to fully condition the OUT rises until the amplifier drives the M1 charge the gate 12V above the source. gate to regulate and limit the output voltage. This is the With the output voltage equal to the input voltage, it is regulate mode. necessary to protect the load from an input supply over- During regulation the excess voltage is dropped across the voltage. In the regulate mode, the overvoltage regulation MOSFET. To prevent overheating the MOSFET, the LTC4366 amplifier is referenced to the output through a 1.23V limits the overvoltage regulation time using the TIMER pin. reference. If the voltage drop across the upper feedback The TIMER pin is charged with 9µA until the pin exceeds resistor, RFB1, exceeds 1.23V the regulation amplifier pulls 2.8V. At that point an overvoltage fault is set, the MOSFET the gate down to regulate the RFB1 voltage back to 1.23V. is turned off, and the part enters a cool-down period of Therefore, the output voltage is clamped by setting the 9 seconds. The logic and timer block are active during proper ratio between RFB1 and RFB2. cool down while the GATE pin is pulled to OUT. For example, if the output voltage is regulated at 100V then The latched-off version, LTC4366-1, will remain in fault the voltage drop across the RFB2 is 98.77V. If the Zener Z3 until the SD pin is toggled low and then high. Once the fault is 5.7V then the voltage drop across RSS is 94.3V. There- is cleared, the GATE is permitted to turn the MOSFET on fore, when the output is at a high voltage, the majority of again. The auto-retry version, LTC4366-2, waits 9 seconds the voltage is dropped across the two resistors RFB2 and then clears the fault and restarts. RSS. This demonstrates how the LTC4366 floats up with the supply. The adjustable 3-terminal regulators, such as the LT®1085 and LM117, are also based on this idea. The Functional Diagram shows the actual circuits. An external RIN resistor on the VDD pin powers up the 12V shunt regulator which then powers up logic supply, VCC. After verifying that the shutdown input is not active, the GATE pin is charged with a 7.5µA current from VDD. This is the start mode. 436612fe 10 For more information www.linear.com/LTC4366 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Pin Functions Simplified Diagram Functional Diagram Operation Applications Information Package Description Typical Application Related Parts