Datasheet LTM8020 (Analog Devices) - 9

LTM8020
APPLICATIONS INFORMATION PCB Layout Positive-to-Negative Voltage Regulation
Most of the headaches associated with PCB layout have The LTM8020 can generate a negative output by tying the been alleviated or even eliminated by the high level of VOUT pads to system ground and connecting GND as shown integration of the LTM8020. The LTM8020 is never-the- in the Typical Applications section. In this configuration, less a switching power supply, and care must be taken to SHDN must be level shifted or referenced to GND, and the minimize EMI and ensure proper operation. Even with the available output current may be reduced. high level of integration, you may fail to achieve specified operation with a haphazard or poor layout. See Figure 3
Hot-Plugging Safely
for a suggested layout. The small size, robustness and low impedance of ceramic Ensure that the grounding and heat sinking are acceptable. capacitors make them an attractive option for the input A few rules to keep in mind are: bypass capacitor of LTM8020. However, these capacitors can cause problems if the LTM8020 is plugged into a live 1. Place the CIN capacitor as close as possible to the VIN supply (see Linear Technology Application Note 88 for and GND connection of the LTM8020. a complete discussion). The low loss ceramic capacitor 2. Place the COUT capacitor as close as possible to the combined with stray inductance in series with the power VOUT and GND connection of the LTM8020. source forms an under damped tank circuit, and the volt- 3. Place the C age at the VIN pin of the LTM8020 can ring to twice the IN and COUT capacitors such that their ground current flows directly adjacent or underneath nominal input voltage, possibly exceeding the LTM8020’s the LTM8020. rating and damaging the part. If the input supply is poorly controlled or the user will be plugging the LTM8020 into 4. Connect all of the GND connections to as large a copper an energized supply, the input network should be designed pour or plane area as possible on the top layer. Avoid to prevent this overshoot. Figure 4 shows the waveforms breaking the ground connection between the external that result when an LTM8020 circuit is connected to a 24V components and the LTM8020. supply through six feet of 24-gauge twisted pair. The first 5. The copper pours also serve as the heat sink for the plot is the response with a 2.2µF ceramic capacitor at the LTM8020. Place several vias in the GND plane to act as input. The input voltage rings as high as 35V and the input heat pipes to other layers of the printed circuit board. current peaks at 20A. One method of damping the tank circuit is to add another capacitor with a series resistor to the circuit. In Figure 4b an aluminum electrolytic capacitor VIN VOUT has been added. This capacitor’s high equivalent series resistance damps the circuit and eliminates the voltage SHDN CIN BIAS COUT overshoot. The extra capacitor improves low frequency ripple filtering and can slightly improve the efficiency of the circuit, though it is likely to be the largest component in the ADJ circuit. An alternative solution is shown in Figure 4c. A 1W GND COPPER resistor is added in series with the input to eliminate the VIAs TO GND PLANE RADJ voltage overshoot (it also reduces the peak input current). 8020 F03 A 0.1µF capacitor improves high frequency filtering. This
Figure 3. Layout Showing Suggested External
solution is smaller and less expensive than the electrolytic
Components, GND Plane and Thermal Vias
capacitor. For high input voltages its impact on efficiency is minor, reducing efficiency less than one-half percent for a 5V output at full load operating from 24V. 8020fe For more information www.linear.com/LTM8020 9