Datasheet LTM4637 (Analog Devices) - 17

LTM4637
applicaTions inForMaTion
JUNCTION-TO-AMBIENT THERMAL RESISTANCE COMPONENTS JUNCTION-TO-CASE (TOP) CASE (TOP)-TO-AMBIENT RESISTANCE RESISTANCE JUNCTION-TO-BOARD RESISTANCE JUNCTION At JUNCTION-TO-CASE CASE (BOTTOM)-TO-BOARD BOARD-TO-AMBIENT (BOTTOM) RESISTANCE RESISTANCE RESISTANCE 4637 F07 µMODULE DEVICE
Figure 7. Graphical Representation of JESD51-12 Thermal Coefficients
A graphical representation of the aforementioned ther- supplied in this data sheet: (1) Initially, FEA software is mal resistances is given in Figure 7; blue resistances are used to accurately build the mechanical geometry of the contained within the µModule regulator, whereas green LTM4637 and the specified PCB with all of the correct resistances are external to the µModule package. material coefficients along with accurate power loss source As a practical matter, it should be clear to the reader that definitions; (2) this model simulates a software-defined no individual or sub-group of the four thermal resistance JEDEC environment consistent with JESD51-12 to predict parameters defined by JESD51-12 or provided in the Pin power loss heat flow and temperature readings at different Configuration section replicates or conveys normal op- interfaces that enable the calculation of the JEDEC-defined erating conditions of a µModule regulator. For example, thermal resistance values; (3) the model and FEA software in normal board-mounted applications, never does 100% is used to evaluate the LTM4637 with heat sink and airflow; of the device’s total power loss (heat) thermally con- (4) having solved for and analyzed these thermal resis- duct exclusively through the top or exclusively through tance values and simulated various operating conditions bottom of the µModule package—as the standard defines in the software model, a thorough laboratory evaluation for θ replicates the simulated conditions with thermocouples JCtop and θJCbottom, respectively. In practice, power loss is thermally dissipated in both directions away from within a controlled-environment chamber while operat- the package—granted, in the absence of a heat sink and ing the device at the same power loss as that which was airflow, a majority of the heat flow is into the board. simulated. The outcome of this process and due diligence yields the set of derating curves shown in this data sheet. Within the LTM4637, be aware there are multiple power devices and components dissipating power, with a con- The 1V, 2.5V and 5V power loss curves in Figures 8 to 10 sequence that the thermal resistances relative to different can be used in coordination with the load current derating junctions of components or die are not exactly linear with curves in Figures 11 to 20 for calculating an approximate respect to total package power loss. To reconcile this θJA thermal resistance for the LTM4637 with various complication without sacrificing modeling simplicity—but heat sinking and airflow conditions. The power loss also not ignoring practical realities—an approach has been curves are taken at room temperature and are increased taken using FEA software modeling along with laboratory with a multiplicative factor according to the junction testing in a controlled-environment chamber to reason- temperature, which is 1.4 for 120°C. The derating curves ably define and correlate the thermal resistance values are plotted with the output current starting at 20A and the 4637fc For more information www.linear.com/LTM4637 17 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Typical Performance Characteristics Pin Functions Block Diagram Decoupling Requirements Operation Applications Information Typical Applications Package Description Package PHOTO Typical Application Related Parts Design Resources