Datasheet LTM8050 (Analog Devices) - 10

LTM8050
PIN FUNCTIONS PACKAGE ROW AND COLUMN LABELING MAY VARY RUN/SS (Pin L5):
Pull the RUN/SS pin below 0.2V to
AMONG µModule PRODUCTS. REVIEW EACH PACKAGE
shut down the LTM8050. Tie to 2.5V or more for normal
LAYOUT CAREFULLY.
operation. If the shutdown feature is not used, tie this pin
VOUT (Bank 1):
Power Output Pins. Apply the output filter to the VIN pin. RUN/SS also provides a soft-start function; capacitor and the output load between these pins and see the Applications Information section. GND pins.
SYNC (Pin L6):
This is the external clock synchronization
GND (Bank 2):
Tie these GND pins to a local ground plane input. Ground this pin for low ripple Burst Mode operation below the LTM8050 and the circuit components. In most at low output loads. Tie to a stable voltage source greater applications, the bulk of the heat flow out of the LTM8050 than 0.7V to disable Burst Mode operation. Do not leave is through these pads, so the printed circuit design has a this pin floating. Tie to a clock source for synchroniza- large impact on the thermal performance of the part. See tion. Clock edges should have rise and fall times faster the PCB Layout and Thermal Considerations sections for than 1μs. See the Synchronization section in Applications more details. Return the feedback divider (RFB) to this net. Information.
VIN (Bank 3):
The VIN pin supplies current to the LTM8050’s
RT (Pin G7):
The RT pin is used to program the switching internal regulator and to the internal power switch. This frequency of the LTM8050 by connecting a resistor from pin must be locally bypassed with an external, low ESR this pin to ground. Table 2 gives the resistor values that capacitor; see Table 1 for recommended values. correspond to the resultant switching frequency. Minimize the capacitance at this pin.
AUX (Pin G5):
Low Current Voltage Source for BIAS. In many designs, the BIAS pin is simply connected to VOUT.
SHARE (Pin H7):
Tie this to the SHARE pin of another The AUX pin is internally connected to VOUT and is placed LTM8050 when paralleling the outputs. Otherwise, do adjacent to the BIAS pin to ease printed circuit board rout- not connect. ing. Although this pin is internally connected to VOUT, it
PGOOD (Pin J7):
The PGOOD pin is the open-collector is not intended to deliver a high current, so do
not
draw output of an internal comparator. PGOOD remains low until current from this pin to the load. If this pin is not tied to the FB pin is within 10% of the final regulation voltage. BIAS, leave it floating. PGOOD output is valid when VIN is above 3.6V and RUN/SS
BIAS (Pin H5):
The BIAS pin connects to the internal power is high. If this function is not used, leave this pin floating. bus. Connect to a power source greater than 2.8V and less
FB (Pin K7):
The LTM8050 regulates its FB pin to 0.79V. than 25V. If the output is greater than 2.8V, connect this Connect the adjust resistor from this pin to ground. The pin there. If the output voltage is less, connect this to a value of R voltage source between 2.8V and 25V. Also, make sure FB is given by the equation RFB = 394.21/(VOUT – 0.79), where R that BIAS + V FB is in kΩ. IN is less than 72V. 8050fc 10 For more information www.linear.com/LTM8050 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Typical Performance Characteristics Pin Functions Block Diagram Operation Applications Information Typical Applications Package Description Package Photo Related Parts Design Resources